The effect on RISC performance of register set size and structure versus code generation strategy

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The effect on RISC performance of register set size and structure versus code generation strategy

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International Symposium on Computer Architecture archive
Proceedings of the 18th annual international symposium on Computer architecture table of contents

Toronto, Ontario, Canada

Pages: 330 - 339

Year of Publication: 1991

ISBN:0-89791-394-9

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Authors

David G. Bradlee	Department of Computer Science and Engineering, FR-35, University of Washington, Seattle, Washington
Susan J. Eggers	Department of Computer Science and Engineering, FR-35, University of Washington, Seattle, Washington
Robert R. Henry	Tera Computer, 400 N 34th Street, Seattle, WA and Department of Computer Science and Engineering, FR-35, University of Washington, Seattle, Washington

Sponsors

IEEE-CS : Computer Society
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 21, Citation Count: 3

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D. Bailey and J. Barton. The N AS kernel benchmark program. NASA Tech. Memo. 87611, Ames Research Center, NASA, Moffet Field, CA, 1984.
	2	David G. Bradlee , Susan J. Eggers , Robert R. Henry, Integrating register allocation and instruction scheduling for RISCs, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.122-131, April 08-11, 1991, Santa Clara, California, United States
	3	David G. Bradlee , Robert R. Henry , Susan J. Eggers, The Marion system for retargetable instruction scheduling, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.229-240, June 24-28, 1991, Toronto, Ontario, Canada
	4	P. Briggs , K. D. Cooper , K. Kennedy , L. Torczon, Coloring heuristics for register allocation, Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation, p.275-284, June 19-23, 1989, Portland, Oregon, United States
	5	G. J. Chaitin, Register allocation & spilling via graph coloring, Proceedings of the 1982 SIGPLAN symposium on Compiler construction, p.98-105, June 23-25, 1982, Boston, Massachusetts, United States
	6	F. C. Chow, Minimizing register usage penalty at procedure calls, Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation, p.85-94, June 20-24, 1988, Atlanta, Georgia, United States
	7	C. W. Fraser and D. R. Hanson. A code generation interface for ANSI C. Tech. rep. CS-TR-270-90, Dept. of Comp. Sci., Princeton Univ., July 1990.
	8	Philip B. Gibbons , Steven S. Muchnick, Efficient instruction scheduling for a pipelined architecture, Proceedings of the 1986 SIGPLAN symposium on Compiler construction, p.11-16, June 25-27, 1986, Palo Alto, California, United States
	9	J. R. Goodman , W.-C. Hsu, Code scheduling and register allocation in large basic blocks, Proceedings of the 2nd international conference on Supercomputing, p.442-452, June 1988, St. Malo, France [doi>10.1145/55364.55407]
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	11	W. W. Hwu , P. P. Chang, Exploiting parallel microprocessor microarchitectures with a compiler code generator, Proceedings of the 15th Annual International Symposium on Computer architecture, p.45-53, May 30-June 02, 1988, Honolulu, Hawaii, United States
	12	G. Kane. MIPS R2000 RISC Architecture. Prentice Hall, Englewood Cliffs, NJ, 1987.
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	14	Motorola, MC88100 Microprocessors User's Manual, Prentice Hall PTR, Upper Saddle River, NJ, 1989
	15	A. R. Pleszkun , G. S. Sohi, The performance potential of multiple functional unit processors, Proceedings of the 15th Annual International Symposium on Computer architecture, p.37-44, May 30-June 02, 1988, Honolulu, Hawaii, United States
	16	Gurindar S. Sohi , Sriram Vajapeyam, Tradeoffs in instruction format design for horizontal architectures, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.15-25, April 03-06, 1989, Boston, Massachusetts, United States
	17	R. M. Stallman. Using and Porting GNU CC. Free Software Foundation, Inc., Cambridge, MA, 1989.
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CITED BY 3

	Carl A. Waldspurger , William E. Weihl, Register relocation: flexible contexts for multithreading, ACM SIGARCH Computer Architecture News, v.21 n.2, p.120-130, May 1993
	Samarina Makhdoom , Daniel Tabak , Richard Auletta, Register/ file/ cache microarchitecture study using VHDL, Proceedings of the 24th annual international symposium on Microarchitecture, p.217-222, September 1991, Albuquerque, New Mexico, Puerto Rico
	David G. Bradlee , Robert R. Henry , Susan J. Eggers, The Marion system for retargetable instruction scheduling, ACM SIGPLAN Notices, v.26 n.6, p.229-240, June 1991