Comparative evaluation of latency reducing and tolerating techniques

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Sarita V. Adve , Mark D. Hill, Weak ordering—a new definition, Proceedings of the 17th annual international symposium on Computer Architecture, p.2-14, May 28-31, 1990, Seattle, Washington, United States
	2	A. Agarwal, PERFORMANCE TRADEOFFS IN MULTITHREADED PROCESSORS, Massachusetts Institute of Technology, Cambridge, MA, 1991
	3	Anant Agarwal , Beng-Hong Lim , David Kranz , John Kubiatowicz, APRIL: a processor architecture for multiprocessing, Proceedings of the 17th annual international symposium on Computer Architecture, p.104-114, May 28-31, 1990, Seattle, Washington, United States
	4	James Archibald , Jean-Loup Baer, Cache coherence protocols: evaluation using a multiprocessor simulation model, ACM Transactions on Computer Systems (TOCS), v.4 n.4, p.273-298, Nov. 1986 [doi>10.1145/6513.6514]
	5	M. Dubois , C. Scheurich , F. Briggs, Memory access buffering in multiprocessors, Proceedings of the 13th annual international symposium on Computer architecture, p.434-442, June 02-05, 1986, Tokyo, Japan
	6	S. J. Eggers , R. H. Katz, Evaluating the performance of four snooping cache coherency protocols, Proceedings of the 16th annual international symposium on Computer architecture, p.2-15, April 1989, Jerusalem, Israel
	7	Kourosh Gharachorloo , Anoop Gupta , John Hennessy, Performance evaluation of memory consistency models for shared-memory multiprocessors, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.245-257, April 08-11, 1991, Santa Clara, California, United States
	8	Kourosh Gharachorloo , Daniel Lenoski , James Laudon , Phillip Gibbons , Anoop Gupta , John Hennessy, Memory consistency and event ordering in scalable shared-memory multiprocessors, Proceedings of the 17th annual international symposium on Computer Architecture, p.15-26, May 28-31, 1990, Seattle, Washington, United States
	9	Stephen R. Goldschmidt , Helen Davis, Tango introduction and tutorial, Stanford University, Stanford, CA, 1990
	10	J. R. Goodman. Cache consistency and sequential consistency. Technical Report no. 61, SCI Committee, March 1989.
	11	Edward H. Gornish , Elana D. Granston , Alexander V. Veidenbaum, Compiler-directed data prefetching in multiprocessors with memory hierarchies, Proceedings of the 4th international conference on Supercomputing, p.354-368, June 11-15, 1990, Amsterdam, The Netherlands
	12	R. H. Halstead, Jr. , T. Fujita, MASA: a multithreaded processor architecture for parallel symbolic computing, Proceedings of the 15th Annual International Symposium on Computer architecture, p.443-451, May 30-June 02, 1988, Honolulu, Hawaii, United States
	13	R. A. Iannucci, Toward a dataflow/von Neumann hybrid architecture, Proceedings of the 15th Annual International Symposium on Computer architecture, p.131-140, May 30-June 02, 1988, Honolulu, Hawaii, United States
	14	David Kroft, Lockup-free instruction fetch/prefetch cache organization, Proceedings of the 8th annual symposium on Computer Architecture, p.81-87, May 12-14, 1981, Minneapolis, Minnesota, United States
	15	L. Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. Comput., C-28(9):241-248, September 1979.
	16	Roland Lun Lee , Duncan H. Lawrie , Pen-Chung Yew, The effectiveness of caches and data prefetch buffers in large-scale shared memory multiprocessors, 1987
	17	R. L. Lee, R-C. Yew, and D. H. Lawrie. Data prefetching in shared memory multiprocessors. In Proc. Int. Conf. Paral. Proc., pages 28--31, August 1987.
	18	Daniel Lenoski , James Laudon , Kourosh Gharachorloo , Anoop Gupta , John Hennessy, The directory-based cache coherence protocol for the DASH multiprocessor, Proceedings of the 17th annual international symposium on Computer Architecture, p.148-159, May 28-31, 1990, Seattle, Washington, United States
	19	Ewing Lusk , James Boyle , Ralph Butler , Terrence Disz , Barnett Glickfeld , Ross Overbeek , James Patterson , Rick Stevens, Portable programs for parallel processors, Holt, Rinehart & Winston, Austin, TX, 1988
	20	J. D. McDonald and D. Baganoff. Vectorization of a particle simulation method for hypersonic ratified flow. In A/AA Thermodynamics, Plasmadynamics and Lasers Conference, June 1988.
	21	Todd Mowry , Anoop Gupta, Tolerating latency through software-controlled prefetching in shared-memory multiprocessors, Journal of Parallel and Distributed Computing, v.12 n.2, p.87-106, June 1991 [doi>10.1016/0743-7315(91)90014-Z]
	22	G. F. Pfister, W. C. Brantley, D. A. George, S. L. Harvey, W. J. Kleinfelder, K. R McAuliffe, E. A. Melton, V. A. Norton, and J. Weiss. The IBM research parallel processor prototype (RP3): Introduction and architecture. In Proc. Int. Conf. Paral. Proc., pages 764-771, 1985.
	23	Allan Kennedy Porterfield , K. W. Kennedy, Software methods for improvement of cache performance on supercomputer applications, 1989
	24	R. Saavedra-Barrera , D. Culler , T. von Eicken, Analysis of multithreaded architectures for parallel computing, Proceedings of the second annual ACM symposium on Parallel algorithms and architectures, p.169-178, July 02-06, 1990, Island of Crete, Greece [doi>10.1145/97444.97683]
	25	G. E. Schmidt. The Butterfly parallel processor. In Proc. int. Conf. Supercomputing, pages 362-365, 1987.
	26	B. J. Smith. Architecture and applications of the HEP multiprocessor computer system. SPIE, 298:241-248, 1981.
	27	Larry Soule , Anoop Gupta, Parallel Distributed-Time Logic Simulation, IEEE Design & Test, v.6 n.6, p.32-48, November 1989 [doi>10.1109/54.41672]
	28	J. Torrellas, M. S. Lain, and J. L. Hennessy. Measurement, analysis, and improvement of the cache behavior of shared data in cache coherent multiprocessors. Technical Report CSL- TR-90-412, Stanford University, Feb. 1990.
	29	W.-D. Weber , A. Gupta, Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary results, Proceedings of the 16th annual international symposium on Computer architecture, p.273-280, April 1989, Jerusalem, Israel
	30	A. W. Wilson, Jr., Hierarchical cache/bus architecture for shared memory multiprocessors, Proceedings of the 14th annual international symposium on Computer architecture, p.244-252, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30378]

Collaborative Colleagues:

Anoop Gupta: colleagues

John Hennessy: colleagues

Kourosh Gharachorloo: colleagues

Todd Mowry: colleagues

Wolf-Dietrich Weber: colleagues