Instruction level profiling and evaluation of the IBM/6000

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Instruction level profiling and evaluation of the IBM/6000

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International Symposium on Computer Architecture archive
Proceedings of the 18th annual international symposium on Computer architecture table of contents

Toronto, Ontario, Canada

Pages: 180 - 189

Year of Publication: 1991

ISBN:0-89791-394-9

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Authors

Chriss Stephens	Center for Dependable Systems, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Bryce Cogswell	Center for Dependable Systems, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
John Heinlein	Center for Dependable Systems, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Gregory Palmer	Center for Dependable Systems, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
John P. Shen	Center for Dependable Systems, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA

Sponsors

IEEE-CS : Computer Society
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 14, Citation Count: 11

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Johnson, Superscalar Micr'opvocessor Design. Englewood Cliffs, NJ: Prentice-ttall, Inc., 1991.
	2	D. W. Wall. "Link-time code inodification,'. Digital Western Research Laboratory, Research Report 89/17, Sep. 1989.
	3	Anita Borg , R. E. Kessler , David W. Wall, Generation and analysis of very long address traces, Proceedings of the 17th annual international symposium on Computer Architecture, p.270-279, May 28-31, 1990, Seattle, Washington, United States
	4	A. Borg, R. E. Kessler, G. Lazana, and D. Wall. "Long address traces from RISC machines: Generation and analysis,". Digital Western Research Laboratory, Research Report 89/14, 1989.
	5	David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
	6	P. S. Hauge, ed., IBM Journal of Research and Development. IBM Corporation, Jan. 1990. Special Issue on the RS/6000.
	7	"SPEC newsletter,". Systems Peiformanee Evaluation Cooperative, Spring 1990.
	8	M. Misra, ed., IBM RISC Syslem/6000 Technology. IBM Corporation, 1990. IBM Publication SA23-2619.
	9	"MIPS language programmer's guide:,'. MIPS Computer Systems, Inc., 1986.
	10	IBM RISC System/6000, XL C Use,"s Guide. IBM Corporation, 1990. IBM Publication SC09- 1259.
	11	N. P. Jouppi, The Nonuniform Distribution of Instruction-Level and Machine Parallelism and its Effect on Performance, IEEE Transactions on Computers, v.38 n.12, p.1645-1658, December 1989 [doi>10.1109/12.40844]
	12	C. Brian Hall , Kevin O'Brien, Performance characteristics of architectural features of the IBM RISC System/6000, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.303-309, April 08-11, 1991, Santa Clara, California, United States

CITED BY 11

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	A. R. Talcott , W. Yamamoto , M. J. Serrano , R. C. Wood , M. Nemirovsky, The impact of unresolved branches on branch prediction scheme performance, ACM SIGARCH Computer Architecture News, v.22 n.2, p.12-21, April 1994
	Ann Marie Grizzaffi Maynard , Colette M. Donnelly , Bret R. Olszewski, Contrasting characteristics and cache performance of technical and multi-user commercial workloads, ACM SIGPLAN Notices, v.29 n.11, p.145-156, Nov. 1994
	Trung A. Diep , John P. Shen , Mike Phillip, EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors, Proceedings of the 26th annual international symposium on Microarchitecture, p.225-235, December 01-03, 1993, Austin, Texas, United States
	Gary Tyson , Matthew Farrens, Techniques for extracting instruction level parallelism on MIMD architectures, Proceedings of the 26th annual international symposium on Microarchitecture, p.128-137, December 01-03, 1993, Austin, Texas, United States
	Richard A. Uhlig , Trevor N. Mudge, Trace-driven memory simulation: a survey, ACM Computing Surveys (CSUR), v.29 n.2, p.128-170, June 1997
	Trung A. Diep , John Paul Shen, VMW: A Visualization-Based Microarchitecture Workbench, Computer, v.28 n.12, p.57-64, December 1995
	David Bernstein , Doron Cohen , Yuval Lavon , Vladimir Rainish, Performance evaluation of instruction scheduling on the IBM RISC System/6000, ACM SIGMICRO Newsletter, v.23 n.1-2, p.226-235, Dec. 1992
	Kiruthika Selvamani , Tarek M. Taha, Estimating critical region parallelism to guide platform retargeting, Proceedings of the 43rd annual southeast regional conference, March 18-20, 2005, Kennesaw, Georgia
	Margarita Esponda , Raúl Rojas, A graphical comparison of RISC processors, ACM SIGARCH Computer Architecture News, v.20 n.4, p.2-8, Sept. 1992
	Charlton D. Rose , J. Kelly Flanagan, Constructing instruction traces from cache-filtered address traces (CITCAT), ACM SIGARCH Computer Architecture News, v.24 n.5, p.1-8, Dec. 1996