Race-free interconnection networks and multiprocessor consistency

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Race-free interconnection networks and multiprocessor consistency

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International Symposium on Computer Architecture archive
Proceedings of the 18th annual international symposium on Computer architecture table of contents

Toronto, Ontario, Canada

Pages: 106 - 115

Year of Publication: 1991

ISBN:0-89791-394-9

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Authors

Anders Landin	Swedish Institute of Computer Science, SICS, Po. Box 1263, S-164 2S Kista, Sweden
Erik Hagersten	Swedish Institute of Computer Science, SICS, Po. Box 1263, S-164 2S Kista, Sweden
Seif Haridi	Swedish Institute of Computer Science, SICS, Po. Box 1263, S-164 2S Kista, Sweden

Sponsors

IEEE-CS : Computer Society
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 29, Citation Count: 21

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Sarita Adve and Mark Hill, Implementing Sequential Consistency in Cache-Based Systems, In Proc. of the 1990 International Conference on Parallel Processing, August 1990
	2	Sarita V. Adve , Mark D. Hill, Weak ordering—a new definition, Proceedings of the 17th annual international symposium on Computer Architecture, p.2-14, May 28-31, 1990, Seattle, Washington, United States
	3	Sarita Adve and Mark Hill, Weak Ordering - A New Definition And Some Implications, Computer Sciences Technical report #902, University of Wisconsin, December 1989
	4	M. Dubois , C. Scheurich , F. Briggs, Memory access buffering in multiprocessors, Proceedings of the 13th annual international symposium on Computer architecture, p.434-442, June 02-05, 1986, Tokyo, Japan
	5	Kourosh Gharachorloo , Daniel Lenoski , James Laudon , Phillip Gibbons , Anoop Gupta , John Hennessy, Memory consistency and event ordering in scalable shared-memory multiprocessors, Proceedings of the 17th annual international symposium on Computer Architecture, p.15-26, May 28-31, 1990, Seattle, Washington, United States
	6	Kourosh Gharachorloo , Anoop Gupta , John Hennessy, Performance evaluation of memory consistency models for shared-memory multiprocessors, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.245-257, April 08-11, 1991, Santa Clara, California, United States
	7	James R. Goodman, Cache Consistency and Sequentim Consistency, Technical Report 61, SCI Committee, March 1989
	8	Erik Hagersten, Anders Landin and Seif Haridi, Multiprocessor Consistency and Synchronization thru Transient Cache States, In Proc. of the Workshop on Scalable Shared-Memory Architectures, Kluwer Academic Publisher, Norwell, Mass, 1991
	9	Erik Hagersten, Anders Landin, Seif Haridi and David Warren, Moving the Shared Memory Closer to the Processors - DDM, Swedish Institute of Computer Science, Technical Report, November 1990
	10	Erik I-Iagersten, Seif I-Iaridi and David Warren, The Cache-Coherence Protocol of the Data Diffusion Machine, In Proc. of the Cache and Interconnect Workshop, Kluwer Academic Publisher, Norwell, Mass, 1990
	11	Leslie Lamport, How to Make a Multiprocessor Computer That Correctly Executes Multiprocessor Programs, IEEE Transactions on Computers C-28 (1979), 690-691
	12	Anders Landin, Erik I-Iagersten and Seif I-Iaridi, Partial Access Orders and Sequential Consistency, Swedish Institute of Computer Science, Technical Report, March 1991
	13	Daniel Lenoski , James Laudon , Kourosh Gharachorloo , Anoop Gupta , John Hennessy, The directory-based cache coherence protocol for the DASH multiprocessor, Proceedings of the 17th annual international symposium on Computer Architecture, p.148-159, May 28-31, 1990, Seattle, Washington, United States
	14	Larry Rudolph , Zary Segall, Dynamic decentralized cache schemes for mimd parallel processors, Proceedings of the 11th annual international symposium on Computer architecture, p.340-347, January 1984
	15	C. E. Scheurich, Access ordering and coherence in shared memory multiprocessors, University of Southern California, Los Angeles, CA, 1989
	16	C. Scheurich , M. Dubois, Correct memory operation of cache-based multiprocessors, Proceedings of the 14th annual international symposium on Computer architecture, p.234-243, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30377]
	17	Per StenstrSm and Fredrik Dahlgren, Personal communication. November 1990
	18	David H. D. Warren and Seif Haridi, Data Diffusion Machine- A Scalable Shared Virtual Memory Multiprocessor. In Proc. of the International Conference on Fifth Generation Computer Systems 1988. ICOT, 1988

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	Craig Williams , Paul F. Reynolds , Bronis R. de Supinski, Delta Coherence Protocols, IEEE Concurrency, v.8 n.3, p.23-29, July 2000
	E. Ender Bilir , Ross M. Dickson , Ying Hu , Manoj Plakal , Daniel J. Sorin , Mark D. Hill , David A. Wood, Multicast snooping: a new coherence method using a multicast address network, ACM SIGARCH Computer Architecture News, v.27 n.2, p.294-304, May 1999
	Kourosh Gharachorloo , Madhu Sharma , Simon Steely , Stephen Van Doren, Architecture and design of AlphaServer GS320, ACM SIGPLAN Notices, v.35 n.11, p.13-24, Nov. 2000
	Kourosh Gharachorloo , Madhu Sharma , Simon Steely , Stephen Van Doren, Architecture and design of AlphaServer GS320, ACM SIGARCH Computer Architecture News, v.28 n.5, p.13-24, Dec. 2000
	Milo M. K. Martin , Daniel J. Sorin , Anastassia Ailamaki , Alaa R. Alameldeen , Ross M. Dickson , Carl J. Mauer , Kevin E. Moore , Manoj Plakal , Mark D. Hill , David H. Wood, Timestamp snooping: an approach for extending SMPs, ACM SIGPLAN Notices, v.35 n.11, p.25-36, Nov. 2000
	Andrew A. Chien , Jae H. Kim, Planar-adaptive routing: low-cost adaptive networks for multiprocessors, ACM SIGARCH Computer Architecture News, v.20 n.2, p.268-277, May 1992
	Melanie L. Fulgham , Lawrence Snyder, Triplex: a multi-class routing algorithm, Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures, p.127-138, June 23-25, 1997, Newport, Rhode Island, United States
	Andrew A. Chien , Jae H. Kim, Planar-adaptive routing: low-cost adaptive networks for multiprocessors, Journal of the ACM (JACM), v.42 n.1, p.91-123, Jan. 1995
	Milo M. K. Martin , Mark D. Hill , David A. Wood, Token coherence: decoupling performance and correctness, ACM SIGARCH Computer Architecture News, v.31 n.2, May 2003
	Y. M. Teo , B. S. S. Onggo, A Framework for Formalization and Strictness Analysis of Simulation Event Orderings, Simulation, v.81 n.4, p.325-335, April 2005
	Harjinder S. Sandhu, Consistency and event ordering in the shared regions model, Proceedings of the 1993 conference of the Centre for Advanced Studies on Collaborative research: distributed computing, October 24-28, 1993, Toronto, Ontario, Canada
	Milo M. K. Martin , Daniel J. Sorin , Anatassia Ailamaki , Alaa R. Alameldeen , Ross M. Dickson , Carl J. Mauer , Kevin E. Moore , Manoj Plakal , Mark D. Hill , David A. Wood, Timestamp snooping: an approach for extending SMPs, ACM SIGARCH Computer Architecture News, v.28 n.5, p.25-36, Dec. 2000
	Harold W. Cain , Mikko H. Lipasti, Memory Ordering: A Value-Based Approach, IEEE Micro, v.24 n.6, p.110-117, November 2004
	Erik Hagersten , Anders Landin , Seif Haridi, DDM: A Cache-Only Memory Architecture, Computer, v.25 n.9, p.44-54, September 1992
	Chaiyasit Manovit , Sudheendra Hangal, Efficient algorithms for verifying memory consistency, Proceedings of the seventeenth annual ACM symposium on Parallelism in algorithms and architectures, July 18-20, 2005, Las Vegas, Nevada, USA
	Harold W. Cain , Mikko H. Lipasti, Verifying sequential consistency using vector clocks, Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures, August 10-13, 2002, Winnipeg, Manitoba, Canada
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	Ehsan Atoofian , Amirali Baniasadi, Using supplier locality in power-aware interconnects and caches in chip multiprocessors, Journal of Systems Architecture: the EUROMICRO Journal, v.54 n.5, p.507-518, May, 2008
	Harold W. Cain , Mikko H. Lipasti, Memory Ordering: A Value-Based Approach, ACM SIGARCH Computer Architecture News, v.32 n.2, p.90, March 2004
	Sudheendra Hangal , Durgam Vahia , Chaiyasit Manovit , Juin-Yeu Joseph Lu, TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model, ACM SIGARCH Computer Architecture News, v.32 n.2, p.114, March 2004