Asynchronous circuit design on reconfigurable devices

ABSTRACT

This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full adders and ripple carry adders, as well as self-timed ring based applications. The comparison analysis has been carried out by prototyping the circuits on standard programmable logic devices, and using the development tools provided by vendors. Although the feasibility of asynchronous circuits has been demonstrated in such devices, the experimental results clearly show the inefficiency of such a kind of digital system implementation. This is mainly due to the architecture characteristics of the programmable devices and the logic synthesis realized by the development environments. Remarks and suggestions are derived from this study for a new FPGA architecture devoted to asynchronous design.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Sequential circuits; Logic arrays

General Terms:
Design, Experimentation, Performance, Reliability, Theory

Keywords:
FPGAs, asynchronous circuits