Design space exploration for 3D architectures

ABSTRACT

As technology scales, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. Increasing interconnect costs make it necessary to consider alternate ways of building modern microprocessors. One promising option is 3D architectures where a stack of multiple device layers with direct vertical tunneling through them are put together on the same chip. As fabrication of 3D integrated circuits has become viable, developing CAD tools and architectural techniques is imperative to explore the design space to 3D microarchitectures. In this article, we give a brief introduction to 3D integration technology, discuss the EDA design tools that can enable the adoption of 3D ICs, and present the implementation of various microprocessor components using 3D technology. An industrial case study is presented as an initial attempt to design 3D microarchitectures.

REFERENCES

• 1: Albayraktaroglu, K., Jalell, A., Wu, X., Franklin, M., Jacob, B., Tseng, C.-W., and Yeung, D. 2005. Biobench: A benchmark suite of bioinformatics applications. In Proceedings of the International Symposium on Performance Analysis of Systems and Software. Austin, TX. 2--9.
• 2: Todd Austin , Eric Larson , Dan Ernst, SimpleScalar: An Infrastructure for Computer System Modeling, Computer, v.35 n.2, p.59-67, February 2002 [doi>10.1109/2.982917]
• 3: Todd M. Austin , Scott E. Breach , Gurindar S. Sohi, Efficient detection of all pointer and array access errors, Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation, p.290-301, June 20-24, 1994, Orlando, Florida, United States
• 4: Bernstein, K. 2006. Introduction to 3d integration. In International Solid State Circuits Conference Tutorial.
• 5: Brent, R. P. and Kung, H. T. 1982. A regular layout for parallel adders. IEEE Trans. Comput., 260--264.
• 6: Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu, B*-Trees: a new representation for non-slicing floorplans, Proceedings of the 37th conference on Design automation, p.458-463, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337541]
• 7: Chris C. N. Chu , D. F. Wong, A matrix synthesis approach to thermal placement, Proceedings of the 1997 international symposium on Physical design, p.163-168, April 14-16, 1997, Napa Valley, California, United States [doi>10.1145/267665.267708]
• 8: J. Cong , Jie Wei , Yan Zhang, A thermal-driven floorplanning algorithm for 3D ICs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.306-313, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382591]
• 9: Shamik Das , Andy Fan , Kuan-Neng Chen , Chuan Seng Tan , Nisha Checka , Rafael Reif, Technology, performance, and computer-aided design of three-dimensional integrated circuits, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA [doi>10.1145/981066.981091]
• 10: W. Rhett Davis , John Wilson , Stephen Mick , Jian Xu , Hao Hua , Christopher Mineo , Ambarish M. Sule , Michael Steer , Paul D. Franzon, Demystifying 3D ICs: The Pros and Cons of Going Vertical, IEEE Design & Test, v.22 n.6, p.498-510, November 2005 [doi>10.1109/MDT.2005.136]
• 11: Yangdong (Steven) Deng , Wojciech Maly, 2.5D system integration: a design driven system implementation schema, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.450-455, January 27-30, 2004, Yokohama, Japan
• 12: Brent Goplen , Sachin Sapatnekar, Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.86, November 09-13, 2003 [doi>10.1109/ICCAD.2003.60]
• 13: Gupta, S., Hilbert, M., Hong, S., and Patti, R. 2004. Techniques for producing 3d ics with high-density interconnect. In Proceedings of the 21st International VLSI Multilevel Interconnection Conference. Waikoloa Beach, HI.
• 14: M. R. Guthaus , J. S. Ringenberg , D. Ernst , T. M. Austin , T. Mudge , R. B. Brown, MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on, p.3-14, December 02-02, 2001 [doi>10.1109/WWC.2001.15]
• 15: Payman Zarkesh-Ha , Jeffrey A. Davis , James D. Meindl, Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.6, p.649-659, Dec. 2000 [doi>10.1109/92.902259]
• 16: John L. Hennessy , David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 2003
• 17: Hinton, G., Sager, D., Upton, M., Boggs, D., Carmean, D., Kyler, A., and Roussel, P. 2001. The microarchitecture of the pentium 4 processor. Intel Techn. J.
• 18: W.-L. Hung , G. M. Link , Yuan Xie , N. Vijaykrishnan , M. J. Irwin, Interconnect and Thermal-aware Floorplanning for 3D Microprocessors, Proceedings of the 7th International Symposium on Quality Electronic Design, p.98-104, March 27-29, 2006 [doi>10.1109/ISQED.2006.77]
• 19: Norman P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, Proceedings of the 17th annual international symposium on Computer Architecture, p.364-373, May 28-31, 1990, Seattle, Washington, United States
• 20: Jung, S. M., Jang, J., Cho, W., Moon, J., Kwak, K., Choi, B., Hwang, B., Lim, H., Jeong, J., Kim, J., and Kim, K. 2004. The revolutionary and truly 3-dimentional 25F2 SRAM technology with the smallest S3 cell, 0.16um2 and SSTFF for ultra high density SRAM. VLSI Techn. Dig. Techn. Papers, 228--229.
• 21: Kang, Y. H. Jung, S. M., Jang, J. H., Moon, J. H., Cho, W. S., Yeo, C. D., Kwak, K. H., Choi, B. H., Hwang, B. J., Jung, W. R., Kim, S. J., Kim, J. H., Na, J. H., Lim, H., Jeong, J. H., and Kim, K. 2004. Fabrication and characteristics of novel load PMOS SSTFT (stacked single-crystal thin film transistor) for 3-dimentional SRAM memory cell. In Proceedings of the IEEE Silicon-on-Insulator Conference (SOI). 127--129.
• 22: Kogge, P. M. and Stone, H. S. 1973. A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Trans. Comput., 786--793.
• 23: Larson, E., Chatterjee, S., and Austin, T. 2001. Mase: A novel infrastructure for detailed microarchitectural modeling. In Proceedings of the International Symposium on Performance Analysis of Systems and Software. Tucson, AZ. 1--9.
• 24: Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 25: Lee, K. W. Nakqmura, T., Ono, T., Yamada, Y., Mozukusa, T., Hashimoto, H., Park, K. T., Kuring, H., and Koyanag, N. 2000. Three-dimensional shared memory fabricated using wafer stacking technology. International Electron Devides Meeting (IEDM). Technical Digest, 165--168.
• 26: G. M. Link , N. Vijaykrishnan, Thermal Trends in Emerging Technologies, Proceedings of the 7th International Symposium on Quality Electronic Design, p.625-632, March 27-29, 2006 [doi>10.1109/ISQED.2006.136]
• 27: Mikko H. Lipasti , Brian R. Mestan , Erika Gunadi, Physical Register Inlining, Proceedings of the 31st annual international symposium on Computer architecture, p.325, June 19-23, 2004, München, Germany
• 28: John Mayega , Okan Erdogan , Paul M. Belemjian , Kuan Zhou , John F. McDonald , Russel P. Kraft, 3D direct vertical interconnect microprocessors test vehicle, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA [doi>10.1145/764808.764846]
• 29: Subbarao Palacharla , James E. Smith, Complexity-effective superscalar processors, 1998
• 30: Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
• 31: Kiran Puttaswamy , Gabriel H. Loh, Implementing Caches in a 3D Technology for High Performance Processors, Proceedings of the 2005 International Conference on Computer Design, p.525-532, October 02-05, 2005 [doi>10.1109/ICCD.2005.65]
• 32: Arifur Rahman , Rafael Reif, System-level performance evaluation of three-dimensional integrated circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.6, p.671-678, Dec. 2000 [doi>10.1109/92.902261]
• 33: Fabrication Technologies for Three-Dimensional Integrated Circuits, Proceedings of the 3rd International Symposium on Quality Electronic Design, p.33, March 18-21, 2002
• 34: André Seznec , Stephen Felix , Venkata Krishnan , Yiannakis Sazeides, Design tradeoffs for the Alpha EV8 conditional branch predictor, Proceedings of the 29th annual international symposium on Computer architecture, p.295, May 25-29, 2002, Anchorage, Alaska
• 35: Shiu, P. and Lim, S. K. 2004. Multi-layer floorplanning for reliable system-on-package. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS).
• 36: Shivakumar, P. Shivakumar, P., and Joupp, N. P. 2001. Cacti 3.0: An integrated cache timing, power, and area model. Western Research Lab Research Report.
• 37: Kevin Skadron , Mircea R. Stan , Wei Huang , Sivakumar Velusamy , Karthik Sankaranarayanan , David Tarjan, Temperature-aware microarchitecture, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 38: Sklansky, J. 1960. Conditional sum addition logic. IRE Trans. Electron. Comput. 9, 2 (June), 226--231.
• 39: Shukri J. Souri , Kaustav Banerjee , Amit Mehrotra , Krishna C. Saraswat, Multiple Si layer ICs: motivation, performance analysis, and design implications, Proceedings of the 37th conference on Design automation, p.213-220, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337394]
• 40: Tezzaron Semiconductors. 2005. Tezzaron unveils 3d SRAM. http://www.tezzaron.com.
• 41: Tsai, C. and Kang, S. 2000. Cell-level placement for improving substrate thermal distributio. IEEE Trans. Comput.-Aided Design Integrat. Circuits Syst.
• 42: Yuh-Fang Tsai , Yuan Xie , N. Vijaykrishnan , Mary Jane Irwin, Three-Dimensional Cache Design Exploration Using 3DCacti, Proceedings of the 2005 International Conference on Computer Design, p.519-524, October 02-05, 2005 [doi>10.1109/ICCD.2005.108]
• 43: Xue, L., Liu, C., and Tiwari, S. 2001. Multi-layers with buried structures (mlbs): An approach to three-dimensional integration. In Proceedings of the IEEE International Conference on Silicon On Insulator. 117--118.
• 44: Zhang, K., Bhattacharya, U., Chen, Z., Hamzaogiu, F., Murray, D., Vallepalli, N., Wang, Y., Zheng, B., and Bohr, M. 2004. A SRAM Design on 65nm CMOS technology with Integrated Leakage Reduction Scheme. IEEE Symposium On VLSI Circuit. Digest of Technical Papers, 294--295.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.0 General

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.0 General

General Terms:
Design, Performance

Keywords:
3D integration, hardware, microarchitecture, processor architectures