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Constraint-driven floorplan repair
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 43rd annual Design Automation Conference table of contents
San Francisco, CA, USA
SESSION: Session 62: placement table of contents
Pages: 1103 - 1108  
Year of Publication: 2006
ISBN:1-59593-381-6
Authors
Michael D. Moffitt  University of Michigan, Ann Arbor, MI
Aaron N. Ng  University of Michigan, Ann Arbor, MI
Igor L. Markov  University of Michigan, Ann Arbor, MI
Martha E. Pollack  University of Michigan, Ann Arbor, MI
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 11,   Downloads (12 Months): 32,   Citation Count: 5
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ABSTRACT

Floorplanning algorithms have traditionally underperformed experienced designers, even when relatively simple interconnect metrics are concerned. However, the sheer scale of modern systems on chip makes an all-manual design flow infeasible. In this paper, we propose a new efficient automated approach to the floorplan repair problem, where a set of violated design constraints are satisfied by applying small changes to an existing rough floorplan. Such a floorplan can be produced by a human designer, by a scalable placement algorithm, or result from engineering adjustments to a pre-existing floorplan. In all cases, overlapping modules must be separated, and in some instances, modules may need to be repositioned to satisfy other requirements.The algorithmic framework we propose is built upon an expressive graph-based encoding of constraints. While capable of representing floorplans with or without overlapping modules, it can also support the outline of the core area, fixed module locations, region constraints, proximity and alignment constraints, etc. Instead of applying randomized local search in the hope of satisfying these constraints, we track all implications of imposed constraints and resolve violations by invoking gradual modifications to the floorplan.The primary focus of this paper is on a particularly efficient conflict-directed algorithm for floorplan repair and legalization. It is shown to completely eliminate overlaps from layouts produced by Capo 9.4, Feng Shui 5.1 and APlace 2.01 on IBM-HB benchmarks with hard blocks, typically requiring negligible runtime and increasing interconnect length by only several percent. Furthermore, we are able to generate legal solutions for these instances that surpass previously reported results in wirelength by an average of roughly 7%.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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S. N. Adya and I. L. Markov. Fixed-outline Floorplanning: Enabling Hierarchical Design. In IEEE Trans. on VLSI Systems, vol. 11(6), pages 1120--1135, 2003.
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J. Cong, M. Romesis, and J. Shinnerl. Fast floorplanning by look-ahead enabled recursive bipartitioning. Technical Report TR040043, Computer Science Dept., UCLA, 2004.
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D. Hill. Method and system for high speed detailed placement of cells within an integrated circuit design, US Patent 6370673, April 2002.
 
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Y. Liao and C. K. Wong. An algorithm to compact a VLSI symbolic layout with mixed constraints. In IEEE Transactions on CAD, Vol. 2, No. 2, 1983.
 
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M. D. Moffitt and M. E. Pollack. Optimal rectangle packing: a meta-CSP approach. To appear in Proc. of ICAPS '06, 2006.
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Collaborative Colleagues:
Michael D. Moffitt: colleagues
Aaron N. Ng: colleagues
Igor L. Markov: colleagues
Martha E. Pollack: colleagues