Standard cell library optimization for leakage reduction

ABSTRACT

Scaling device geometries have caused leakage-power consumption to be one of the major challenges of deep sub-micron design and a major source for parametric yield loss. We propose a library optimization approach involving generation of additional variants for each cell master, by biasing gate-lengths of devices. We employ transistor-level gate-length assignment to exploit asymmetries in standard cell circuit topology as well slack distribution of the design. The enhanced library is used by a power optimizer to reduce design leakage without violating any timing constraints. Such transistor-level optimization of cell libraries offers significantly better leakage-delay tradeoff than simple cell-level biasing (CLB) proposed previously. Experimental results on benchmarks show transistor-level biasing (TLB) can improve the CLB leakage optimization results by 8-17%. There is a corresponding improvement in design leakage distribution as well.

REFERENCES

• 1: S. Narendra et. al., "Leakage Issues in IC Design: Trends, Estimation and Avoidance", Tutorial, ICCAD, 2003.
• 2: S. Mutah, T. Douseki Y. Marsuya, T. Aoki and S. Shigematru. "I-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS, JSSC 1995. Vol. 30. No. 8.00. 847--854.
• 3: Y. Oowalti et al.. "A sub-0.1um Circuit Design with Substrate-Over-Biasing". ISSCC. 1998, pp. 88--89.
• 4: Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Rajendran Panda , David Blaauw, Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.79-90, April 2002 [doi>10.1109/92.994980]
• 5: Puneet Gupta , Andrew B. Kahng , Puneet Sharma, A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology, Proceedings of the 6th International Symposium on Quality of Electronic Design, p.421-426, March 21-23, 2005 [doi>10.1109/ISQED.2005.13]
• 6: Liqiong Wei , Zhanping Chen , Mark Johnson , Kaushik Roy , Vivek De, Design and optimization of low voltage high performance dual threshold CMOS circuits, Proceedings of the 35th annual conference on Design automation, p.489-494, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277179]
• 7: Puneet Gupta , Andrew B. Kahng , Puneet Sharma , Dennis Sylvester, Selective gate-length biasing for cost-effective runtime leakage control, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996661]
• 8: A. Salz , M. Horowitz, IRSIM: an incremental MOS switch-level simulator, Proceedings of the 26th ACM/IEEE conference on Design automation, p.173-178, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74412]
• 9: F. Brglez, D. Bryan, and K. Kozminski, "Combinatorial Profiles of Sequential Benchmark Circuits," Proc. International Symposium on Circuits and Systems (ISCAS), pp. 1229--1234, IEEE, 1989.
• 10: http://www.opencores.org/project

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Design, Performance

Keywords:
gate-length biasing, leakage reduction, library optimization