Computation of accurate interconnect process parameter values for performance corners under process variations

ABSTRACT

This paper introduces a fast analytical model for determining accurate parasitic values for best- and worst-case delays of a stage under interconnect process variations. The inputs to the model are the nominal values for each interconnect and device parameter and the amount of variation in each interconnect parameter. The outputs of the model are the interconnect parameter dimensions within the range of process variation that yield the best- and worst-case delay of a stage. Simulations show that our model accurately predicts the performance corners of a stage while those predicted by traditional best/worst-case analysis methodologies can have an error of up to 28.42%.

REFERENCES

• 1: Kulkarni, M., Nagaraj, N.S., Marshall, A., Viet Le. Impact of Selective Process Bias of Interconnects on Circuit Delay. In Proc. of DCAS (2004), 155--158.
• 2: Michael Orshansky , Linda Milor , Pinhong Chen , Kurt Keutzer , Chenming Hu, Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 3: Louis K. Scheffer, Physical CAD changes to incorporate design for lithography and manufacturability, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.768-773, January 27-30, 2004, Yokohama, Japan
• 4: Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775920]
• 5: Ying Liu , Sani R. Nassif , Lawrence T. Pileggi , Andrzej J. Strojwas, Impact of interconnect variations on the clock skew of a gigahertz microprocessor, Proceedings of the 37th conference on Design automation, p.168-171, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337365]
• 6: Nassif, S.R. Modeling and Analysis of Manufacturing Variations. In IEEE CICC (2001), 223--228.
• 7: J. D. Ma , R. A. Rutenbar, Interval-valued reduced order statistical interconnect modeling, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.460-467, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382621]
• 8: Kanak Agarwal , Dennis Sylvester , David Blaauw , Frank Liu , Sani Nassif , Sarma Vrudhula, Variational delay metrics for interconnect timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996675]
• 9: Farid N. Najm , Noel Menezes, Statistical timing analysis based on a timing yield model, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996696]
• 10: Chang, H., Sapatnekar, S.S. Statistical Timing Analysis Under Spatial Correlation. In TCAD (2005), 1467--1482.
• 11: Power, J.A., Donnellan, B., Mathewson, A., Lane, W.A. Relating Statistical MOSFET Model Parameter Variabilities to IC Manufacturing Process Fluctuations Enabling Realistic Worst Case Design. In IEEE TSM (1994), 306--318.
• 12: Elmore, W.C. The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers. In the Journal of Applied Physics (Jan. 1948), 55--63.
• 13: Sakurai, T., Newton, A.R. Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas. J. of Solid-State Circuits (1990), 584--594.
• 14: Wong, S.-C., Lee, G.-Y., Ma, D.-J. Modeling of Interconnect Capacitance, Delay, and Crosstalk in VLSI. In IEEE TSM (2000), 108--111.
• 15: Xi, X., Dunga, M., He, J., Liu, W., Cao, K.M., Jin, X., Ou, J.J., Chan, M., Niknejad, A.M., Hu, C. BSIM4.5 MOSFET Model - User's Manual. U. of Cal., CA, 2004

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Performance, Reliability, Verification

Keywords:
STA, delay, interconnect, sorners, variations