MARS-C: modeling and reduction of soft errors in combinational circuits

ABSTRACT

Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we present a symbolic framework based on BDDs and ADDs that enables analysis of combinational circuit reliability from different aspects: output susceptibility to error, influence of individual gates on individual outputs and overall circuit reliability, and the dependence of circuit reliability on glitch duration, amplitude, and input patterns. This is demonstrated by the set of experimental results, which show that the mean output error susceptibility can vary from less than 0.1%, for large circuits and small glitches, to about 30% for very small circuits and large enough glitches. The results obtained with the proposed symbolic framework are within 7% average error and up to 5000X speedup when compared to HSPICE detailed circuit simulation. The framework can be used for selective gate sizing targeting radiation hardening which is done only for gates with error impact exceeding a certain threshold. Using such a technique, soft error rate (SER) can be reduced by 25-67% for various threshold values, when applied to a subset of ISCAS'85 and mcnc'91 benchmarks.

REFERENCES

• 1: K. Mohanram and N. A. Touba. Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. In Proc. of International Test Conference (ITC), pp. 893--901, 2003.
• 2: Robert Baumann, Soft Errors in Advanced Computer Systems, IEEE Design & Test, v.22 n.3, p.258-266, May 2005 [doi>10.1109/MDT.2005.69]
• 3: Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
• 4: R. Iris Bahar , Erica A. Frohm , Charles M. Gaona , Gary D. Hachtel , Enrico Macii , Abelardo Pardo , Fabio Somenzi, Algebraic decision diagrams and their applications, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.188-191, November 07-11, 1993, Santa Clara, California, United States
• 5: Chong Zhao , Xiaoliang Bai , Sujit Dey, A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996804]
• 6: Ming Zhang , N. R. Shanbhag, A soft error rate analysis (SERA) methodology, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.111-118, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382553]
• 7: Yuvraj Singh Dhillon , Abdulkadir Utku Diril , Abhijit Chatterjee, Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits, Proceedings of the conference on Design, Automation and Test in Europe, p.288-293, March 07-11, 2005 [doi>10.1109/DATE.2005.274]
• 8: Smita Krishnaswamy , George F. Viamontes , Igor L. Markov , John P. Hayes, Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices, Proceedings of the conference on Design, Automation and Test in Europe, p.282-287, March 07-11, 2005 [doi>10.1109/DATE.2005.47]
• 9: M. Omana, G. Papasso, D. Rossi, and C. Metra. A Model for Transient Fault Propagation in Combinatorial Logic. In Proc. of the 9th IEEE International On-Line Testing Symposium, IOLTS'03, pp. 11--115, July 2003.
• 10: Bin Zhang , Wei-Shen Wang , Michael Orshansky, FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs, Proceedings of the 7th International Symposium on Quality Electronic Design, p.755-760, March 27-29, 2006 [doi>10.1109/ISQED.2006.64]
• 11: P. Liden, P. Dahlgren, R. Johansson, and J. Karlsson. On Latching Probability of Particle Induced Transients in Combinational Networks. In Proc. of Fault-Tolerant Computing Symposium, pp. 340--349, 1994.
• 12: M. P. Baze and S. P. Buchner. Attenuation of Single Event Induced Pulses in CMOS Combinational Logic. In IEEE Transaction on Nuclear Science, Vol. 44, No. 6, pp. 2217--2223, December 1997.
• 13: D. Marculescu , R. Marculescu , M. Pedram, Trace-driven steady-state probability estimation in FSMs with application to power estimation, Proceedings of the conference on Design, automation and test in Europe, p.774-781, February 23-26, 1998, Le Palais des Congrés de Paris, France
• 14: Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
• 15: Quming Zhou , K. Mohanram, Cost-effective radiation hardening technique for combinational logic, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.100-106, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382551]
• 16: Berkeley Predictive Technology Model (BPTM): http://www-device.eecs.berkeley.edu/~ptm.
• 17: Ivan Sutherland , Bob Sproull , David Harris, Logical effort: designing fast CMOS circuits, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1999
• 18: N. Miskov-Zivanov and D. Marculescu. Circuit Reliability Analysis Using Symbolic Techniques.To appear in IEEE Transactions on Computer Aided Design (TCAD), 2006.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Reliability

Keywords:
SER, reliability symbolic techniques