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ABSTRACT

In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of nanowires configured to implement the required LUTs and intra-cluster MUXes. A CMOS interface is also proposed to provide configuration and latching for the nanoscale cluster. Inter-cluster routing is assumed to remain at CMOS scale. Experimental analysis is performed to evaluate area and performance of the hybrid FPGA and results are compared with traditional fully CMOS FPGA (scaled to 22nm). Up to 75% area reduction was obtained from implementing MCNC benchmarks on hybrid FPGA. Performance of the hybrid FPGA is shown to be close to that of CMOS FPGA.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance

Keywords:
FPGA, molecular electronics, reconfigurable nanoscale devices