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Buffer memory optimization for video codec application modeled in Simulink
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 43rd annual Design Automation Conference table of contents
San Francisco, CA, USA
SESSION: Session 39: parallelism and memory optimizations table of contents
Pages: 689 - 694  
Year of Publication: 2006
ISBN:1-59593-381-6
Authors
Sang-Il Han  Seoul National Univ., Seoul, Korea and SLS Group, Grenoble, France
Xavier Guerin  SLS Group, Grenoble, France
Soo-Ik Chae  Seoul National Univ., Seoul, Korea
Ahmed A. Jerraya  SLS Group, Grenoble, France
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and control-dependent, memory optimization based on global and precise analysis of data and control dependency is required. We generate a memory-efficient C code from a restricted Simulink model, which can represent both data and control dependency explicitly, by applying two buffer memory optimization techniques: copy removal and buffer sharing. Copy removal is performed while parsing the Simulink model. Buffer sharing requires global scheduling and formal lifetime analysis. Experimental results on an H.264 video decoder show that the buffer memory size and execution time of the C code generated by the proposed method are 71% and 32% less than those of the C code produced by Simulink's C code generator, respectively. When compared to the hand written C code, the memory size was reduced by 27% while its execution time was increased by only 3%.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
ITU-T and ISO/IEC JTC1, "Advanced video coding for generic audiovisual services," ITU-T Recommendation H.264 - ISO/IEC 14496-10 AVC, 2003.
 
2
P. K. Murthy, and S. S. Bhattacharyya, "Shared Buffer Implementations of Signal Processing Systems Using Lifetime Analysis Techniques," IEEE TCAD, vol. 20, no. 2, Feb., 2001.
 
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H. Oh and S. Ha, "Memory-optimized Software Synthesis from Dataflow Program Graphs with Large Size Data Samples," EURASIP Journal on Applied Signal Processing Vol. 2003 pp 514--529 May 2003.
 
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S. Ritz, M. Willems, and H. Meyr. "Scheduling for optimum data memory compaction in block diagram oriented software synthesis," Proc. of ICASS'95, May 1995.
 
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Real-Time Workshop, http://www.mathworks.com
 
14
Simulink, http://www.mathworks.com
 
15
Tensilica Xtensa V, http://www.tensilica.com


Collaborative Colleagues:
Sang-Il Han: colleagues
Xavier Guerin: colleagues
Soo-Ik Chae: colleagues
Ahmed A. Jerraya: colleagues