| Buffer memory optimization for video codec application modeled in Simulink |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 43rd annual Design Automation Conference
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San Francisco, CA, USA
SESSION: Session 39: parallelism and memory optimizations
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Pages: 689 - 694
Year of Publication: 2006
ISBN:1-59593-381-6
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Authors
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Sang-Il Han
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Seoul National Univ., Seoul, Korea and SLS Group, Grenoble, France
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Xavier Guerin
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SLS Group, Grenoble, France
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Soo-Ik Chae
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Seoul National Univ., Seoul, Korea
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Ahmed A. Jerraya
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SLS Group, Grenoble, France
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Downloads (6 Weeks): 3, Downloads (12 Months): 49, Citation Count: 5
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ABSTRACT
Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and control-dependent, memory optimization based on global and precise analysis of data and control dependency is required. We generate a memory-efficient C code from a restricted Simulink model, which can represent both data and control dependency explicitly, by applying two buffer memory optimization techniques: copy removal and buffer sharing. Copy removal is performed while parsing the Simulink model. Buffer sharing requires global scheduling and formal lifetime analysis. Experimental results on an H.264 video decoder show that the buffer memory size and execution time of the C code generated by the proposed method are 71% and 32% less than those of the C code produced by Simulink's C code generator, respectively. When compared to the hand written C code, the memory size was reduced by 27% while its execution time was increased by only 3%.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 5
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Sang-Il Han , Soo-Ik Chae , Lisane Brisolara , Luigi Carro , Katalin Popovici , Xavier Guerin , Ahmed A. Jerraya , Kai Huang , Lei Li , Xiaolang Yan, Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation, Integration, the VLSI Journal, v.42 n.2, p.227-245, February, 2009
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