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A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 43rd annual Design Automation Conference table of contents
San Francisco, CA, USA
SESSION: Session 36: electrical and thermal issues in FPGAS table of contents
Pages: 618 - 623  
Year of Publication: 2006
ISBN:1-59593-381-6
Authors
David Atienza  DACYA/UCM, Madrid, Spain and LSI/EPFL, Lausanne, Switzerland
Pablo G. Del Valle  DACYA/UCM, Madrid, Spain
Giacomo Paci  DACYA/UCM, Madrid, Spain
Francesco Poletti  DEIS/UNIBO, Bologna, Italy
Luca Benini  DEIS/UNIBO, Bologna, Italy
Giovanni De Micheli  LSI/EPFL, Lausanne, Switzerland
Jose M. Mendias  DACYA/UCM, Madrid, Spain
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 22,   Downloads (12 Months): 83,   Citation Count: 8
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ABSTRACT

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are complex to design as they must execute multiple complex applications (e.g. video processing, 3D games), while meeting additional design constraints (e.g. energy consumption or time-to-market). Moreover, the rise of temperature in the die for MPSoC components can seriously affect their final performance and reliability. Therefore, mechanisms to efficiently evaluate complete HW/SW MPSoC designs in terms of energy consumption, temperature, performance and other key metrics are needed. In this paper, we present a new HW/SW FPGA-based emulation framework that allows designers to rapidly extract a number of critical statistics from processing cores, memories and interconnection systems being emulated on a FPGA. This information is then used to interact in real-time with a SW thermal model running on a host computer via an Ethernet port. The results show speed-ups of three orders of magnitude compared to cycle-accurate MPSoC simulators, which enable a very fast exploration of a large range of MPSoC design alternatives at the cycle-accurate level. Finally, our HW/SW framework allows designers to test run-time thermal management strategies with real-life inputs without any loss in the performance of the emulated system.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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A. Jerraya, et al. Multiprocessor SoCs. Morgan Kaufmann, 2005.
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CITED BY  8

Collaborative Colleagues:
David Atienza: colleagues
Pablo G. Del Valle: colleagues
Giacomo Paci: colleagues
Francesco Poletti: colleagues
Luca Benini: colleagues
Giovanni De Micheli: colleagues
Jose M. Mendias: colleagues