| A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 43rd annual Design Automation Conference
table of contents
San Francisco, CA, USA
SESSION: Session 36: electrical and thermal issues in FPGAS
table of contents
Pages: 618 - 623
Year of Publication: 2006
ISBN:1-59593-381-6
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Authors
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David Atienza
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DACYA/UCM, Madrid, Spain and LSI/EPFL, Lausanne, Switzerland
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Pablo G. Del Valle
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DACYA/UCM, Madrid, Spain
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Giacomo Paci
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DACYA/UCM, Madrid, Spain
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Francesco Poletti
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DEIS/UNIBO, Bologna, Italy
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Luca Benini
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DEIS/UNIBO, Bologna, Italy
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Giovanni De Micheli
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LSI/EPFL, Lausanne, Switzerland
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Jose M. Mendias
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DACYA/UCM, Madrid, Spain
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Downloads (6 Weeks): 22, Downloads (12 Months): 83, Citation Count: 8
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ABSTRACT
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are complex to design as they must execute multiple complex applications (e.g. video processing, 3D games), while meeting additional design constraints (e.g. energy consumption or time-to-market). Moreover, the rise of temperature in the die for MPSoC components can seriously affect their final performance and reliability. Therefore, mechanisms to efficiently evaluate complete HW/SW MPSoC designs in terms of energy consumption, temperature, performance and other key metrics are needed. In this paper, we present a new HW/SW FPGA-based emulation framework that allows designers to rapidly extract a number of critical statistics from processing cores, memories and interconnection systems being emulated on a FPGA. This information is then used to interact in real-time with a SW thermal model running on a host computer via an Ethernet port. The results show speed-ups of three orders of magnitude compared to cycle-accurate MPSoC simulators, which enable a very fast exploration of a large range of MPSoC design alternatives at the cycle-accurate level. Finally, our HW/SW framework allows designers to test run-time thermal management strategies with real-life inputs without any loss in the performance of the emulated system.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 8
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Salvatore Carta , Andrea Acquaviva , Pablo G. Del Valle , David Atienza , Giovanni De Micheli , Fernando Rincon , Luca Benini , Jose M. Mendias, Multi-processor operating system emulation framework with thermal feedback for systems-on-chip, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, p.311-316, March 11-13, 2007, Stresa-Lago Maggiore, Italy
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Srinivasan Murali , Almir Mutapcic , David Atienza , Rajesh Gupta , Stephen Boyd , Giovanni De Micheli, Temperature-aware processor frequency assignment for MPSoCs using convex optimization, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria
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