IMPRES: integrated monitoring for processor reliability and security

ABSTRACT

Security and reliability in processor based systems are concernsrequiring adroit solutions.Securityis often compromised by code injection attacks, jeopardizing even `trusted software'.Reliabilityis of concern where unintended code is executed in modern processors with ever smaller feature sizes and low voltage swings causing bit flips. Countermeasures by software-only approaches increasecodesize by large amounts and therefore significantly reduce performance. Hardware assisted approaches add extensive amountsofhardware monitors and thus incur unacceptably highhardware cost. This paper presents a novel hardware/softwaretechniqueat the granularity of micro-instructions to reduce overheads considerably. Experiments show thatour technique incurs an additional hardware overhead of 0.91% and clock period increase of 0.06%. Average clock cycle and code size overheads are just 11.9% and 10.6% forfive industrystandard application benchmarks. These overheads are far smaller than have been previously encountered.

REFERENCES

• 1: Divya Arora , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha, Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring, Proceedings of the conference on Design, Automation and Test in Europe, p.178-183, March 07-11, 2005 [doi>10.1109/DATE.2005.266]
• 2: Doug Burger , Todd M. Austin, The SimpleScalar tool set, version 2.0, ACM SIGARCH Computer Architecture News, v.25 n.3, p.13-25, June 1997 [doi>10.1145/268806.268810]
• 3: C. Cowan et al. StackGuard: Automatic Adaptive Detection and Prevention of Buffer-Overflow Attacks. In Proc. 7th USENIX Security Conference, pages 63--78, San Antonio, Texas, 1998.
• 4: Joan G. Dyer , Mark Lindemann , Ronald Perez , Reiner Sailer , Leendert van Doorn , Sean W. Smith , Steve Weingart, Building the IBM 4758 Secure Coprocessor, Computer, v.34 n.10, p.57-66, October 2001 [doi>10.1109/2.955100]
• 5: Gunter Ollmann. Second-order Code Injection Attacks: Advanced Code Injection Techniques and Testing Procedures, 2003.
• 6: M. R. Guthaus , J. S. Ringenberg , D. Ernst , T. M. Austin , T. Mudge , R. B. Brown, MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on, p.3-14, December 02-02, 2001 [doi>10.1109/WWC.2001.15]
• 7: Trevor Jim , J. Greg Morrisett , Dan Grossman , Michael W. Hicks , James Cheney , Yanling Wang, Cyclone: A Safe Dialect of C, Proceedings of the General Track: 2002 USENIX Annual Technical Conference, p.275-288, June 10-15, 2002
• 8: R. Lee et al. Enlisting hardware architecture to thwart malicious code injection. In Proceedings of the International Conference on Security in Pervasive Computing. Springer Verlag LNCS, March 2003.
• 9: J. McGregor et al. A processor architecture defense against buffer overflow attacks. In Proceedings of the SPC'03, pages 237--252. Springer Verlag, March 2003.
• 10: George C. Necula, Proof-carrying code, Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.106-119, January 15-17, 1997, Paris, France [doi>10.1145/263699.263712]
• 11: Jorgen Peddersen , Seng Lin Shee , Andhi Janapsatya , Sri Parameswaran, Rapid Embedded Hardware/Software System Generation, Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), p.111-116, January 03-07, 2005 [doi>10.1109/ICVD.2005.145]
• 12: R. G. Ragel and S. Parameswaran. Soft error detection and recovery in application specific instruction-set processors. In Proceedings of the SELSE-1, April 2005.
• 13: Roshan G. Ragel , Sri Parameswaran , Sayed Mohammad Kia, Micro embedded monitoring for security in application specific instruction-set processors, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA [doi>10.1145/1086297.1086337]
• 14: Srivaths Ravi , Anand Raghunathan , Paul Kocher , Sunil Hattangady, Security in embedded systems: Design challenges, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.3, p.461-491, August 2004 [doi>10.1145/1015047.1015049]
• 15: The PEAS Team. ASIP Meister, http://www.eda-meister.org/asip-meister/, 2002.
• 16: The Synopsys Team. Synopsys Design Compiler, The industry standard for logic synthesis. http://www.synopsys.com/.
• 17: D. Wagner et al. A first step towards automated detection of buffer overrun vulnerabilities. In Network and Distributed System Security Symposium, pages 3--17, San Diego, CA, February 2000.
• 18: Glenn Wurster , P. C. van Oorschot , Anil Somayaji, A Generic Attack on Checksumming-Based Software Tamper Resistance, Proceedings of the 2005 IEEE Symposium on Security and Privacy, p.127-138, May 08-11, 2005 [doi>10.1109/SP.2005.2]
• 19: J. Xu et al. Architecture support for defending against buffer overflow attacks. In EASY-2 Workshop, October 2002.
• 20: Y. Younan, W. Joosen, and F. Piessens. Code injection in C and CPP: A Survey of Vulnerabilities and Countermeasure, July 2004.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Design, Performance, Reliability, Security

Keywords:
basic block checksumming, bit flips detection, check sum encryption, detecting code injection attacks