Register binding for clock period minimization

ABSTRACT

In modern high-speed circuit design, the clock skew has been widely utilized as a manageable resource to improve the circuit performance. However, in high-level synthesis stage, the circuit is never optimized for the utilization of clock skew. This paper is the first attempt to the high-level synthesis of non-zero clock skew circuits. First, we show that the register binding in high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions lead to different smallest feasible clock periods. Then, based on that observation, we formulate the problem of register binding for clock period minimization. Given a constraint on the number of registers, our objective is to find a minimum-period register binding solution. Experimental data show that, in most benchmark circuits, the lower bound of the clock period can be achieved without any extra overhead on the number of registers.

REFERENCES

• 1: John P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, v.39 n.7, p.945-951, July 1990 [doi>10.1109/12.55696]
• 2: R.B. Deokar and S.S. Sapatnekar, "A Graph-Theoretic Approach to Clock Skew Optimization," Proc. of IEEE International Symposium on Circuits and Systems, vol. 1, pp. 407--410, 1994.
• 3: C. Albrecht , B. Korte , J. Schietke , J. Vygen, Cycle time and slack optimization for VLSI-chips, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.232-238, November 07-11, 1999, San Jose, California, United States
• 4: F. J. Kurdahi , A. C. Parker, REAL: a program for REgister ALlocation, Proceedings of the 24th ACM/IEEE conference on Design automation, p.210-215, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37920]
• 5: C. Tseng and D.P. Siewiorek, "Automatic Synthesis of Data Paths in Digital Systems," IEEE Trans. on Computer-Aided Design," vol. 5, no. 3, pp. 379--395, 1986.
• 6: Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors, Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02), p.391, September 16-18, 2002
• 7: Deming Chen , Jason Cong, Register binding and port assignment for multiplexer optimization, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.68-73, January 27-30, 2004, Yokohama, Japan
• 8: S.H. Huang and C.H. Cheng, "A Formal Approach to the Slack Driven Scheduling Problem in High Level Synthesis," Proc. of IEEE International Symposium on Circuits and Systems, pp. 5633--5636, 2005.
• 9: Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Automatic synthesis

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Optimization

General Terms:
Algorithms, Design, Performance

Keywords:
clock skew, high-level synthesis, timing optimization