A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS

ABSTRACT

Double-gate CMOS is projected to replace classical bulk and SOI technologies around the 32nm node. Predicting the impact of process variations on yield for these novel devices is necessary at an early stage of the design cycle, to enable optimal technology and circuit design choices. This paper presents a fully physical model for double-gate leakage distribution due to gate length (L) and body thickness (t_si) variations, both for single devices and stacks. The model is derived directly from the solution of Poisson's and Schrödinger's equations, and thus captures the effect of unique double-gate phenomena such as volume inversion and quantum confinement. It is scalable to L=13nm and t_si=3nm, with less than 2% error for 3 σ variation as large as 20% of nominal process parameters.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Design, Theory

Keywords:
double-gate, finFET, leakage distribution, multiple-gate, process variations, tri-gate