| Reliability challenges for 45nm and beyond |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 43rd annual Design Automation Conference
table of contents
San Francisco, CA, USA
SESSION: Session 12: Special Session: reliability challenges for 65NM and beyond
table of contents
Pages: 176 - 181
Year of Publication: 2006
ISBN:1-59593-381-6
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Downloads (6 Weeks): 10, Downloads (12 Months): 91, Citation Count: 3
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ABSTRACT
Scaling, for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits.This will require that designers will have to be very careful with: high current densities,voltage overshoots, localized hot spots on the chip, high duty-cycle applications, and high thermal-resistance packaging.In addition to the reliability issues, interconnect RC time-delay will worsen with scaling because Cu resistivity is expected to increase due to surface and grain boundary scattering in very narrow interconnects.Also, the low-k interconnect-dielectric introduction rate has been much slower than ITRS roadmap forecasts.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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