Timing driven power gating

ABSTRACT

Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current (MIC) through sleep transistors. In this paper, we propose a new methodology for determining the size of sleep transistors for the DSTN structure. We present novel algorithms and theorems for efficiently estimating a tight upper bound of the voltage drop. We also present efficient heurists for minimizing the sizes of sleep transistors. Our experimental results are very exciting.

REFERENCES

• 1: Mohab Anis , Mohamed Mahmoud , Mohamed Elmasry , Shawki Areibi, Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514041]
• 2: Cheng-Tao Hsieh , Jian-Cheng Lin , Shih-Chieh Chang, A vectorless estimation of maximum instantaneous current for sequential circuits, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.537-540, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382636]
• 3: Jiang, Y.M., and et al., "Estimation of Maximum Power and Instantaneous Current using a Genetic Algorithm," Proc. of the Custom Integrated Circuits Conf, pp. 135--138, 1997.
• 4: Angela Krstić , Kwang-Ting Cheng, Vector generation for maximum instantaneous current through supply lines for CMOS circuits, Proceedings of the 34th annual conference on Design automation, p.383-388, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266176]
• 5: James Kao , Anantha Chandrakasan , Dimitri Antoniadis, Transistor sizing issues and tool for multi-threshold CMOS technology, Proceedings of the 34th annual conference on Design automation, p.409-414, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266182]
• 6: James Kao , Siva Narendra , Anantha Chandrakasan, MTCMOS hierarchical sizing based on mutual exclusive discharge patterns, Proceedings of the 35th annual conference on Design automation, p.495-500, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277180]
• 7: James Kao , Siva Narendra , Anantha Chandrakasan, Subthreshold leakage modeling and reduction techniques, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.141-148, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774593]
• 8: Changbo Long , Lei He, Distributed sleep transistor network for power reduction, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775879]
• 9: Mutoh, S., and et al., "1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS," IEEE JSSC, vol. 30, no. 8, pp. 847--854, Aug. 1995.
• 10: Roy, K., Mukhopadhyay, S., and Mahmoodi-Meimand, H., "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits," Proc. of the IEEE, vol. 91, no. 2, pp. 305--327, Feb. 2003.
• 11: Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Jingyan Zuo , Abhijit Dharchoudhury , Rajendran Panda , David Blaauw, Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing, Proceedings of the 36th ACM/IEEE conference on Design automation, p.436-441, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309975]
• 12: Tschanz, J. W., and et al., "Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors," IEEE JSSC, vol. 38, no. 11, pp. 1838--1845, Nov. 2003.
• 13: Liqiong Wei , Zhanping Chen , Kaushik Roy , Mark C. Johnson , Yibin Ye , Vivek K. De, Design and optimization of dual-threshold circuits for low-voltage low-power applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.16-24, March 1999 [doi>10.1109/92.748196]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance

Keywords:
IR drop, leakage current, power gating