Towards a C++-based design methodology facilitating sequential equivalence checking

ABSTRACT

It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). These models are written in C++ primarily because it is possible to achieve very high simulation speeds, but also because it is productive to code at high levels of abstraction. In this paper we present a modeling methodology that continues to exploit the inherent advantages of writing models in C++ while ensuring that they are usable for formal verification of RTL through the use of sequential equivalence checking technology. An industrial case study is presented to show the validity of the approach.

REFERENCES

• 1: David Maliniak, "Equivalence Checker Handles Sequential Logic", Electronic Design, May 12, 2005
• 2: Frank Ghenassia (ed), "Transaction Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems", Springer 1st Edition, 2005

INDEX TERMS

Primary Classification:
  I. Computing Methodologies
  I.6 SIMULATION AND MODELING
      I.6.5 Model Development
          Subjects: Modeling methodologies

General Terms:
Languages, Verification

Keywords:
modeling methodology, sequential equivalence checking