| Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 43rd annual Design Automation Conference
table of contents
San Francisco, CA, USA
SESSION: Session 5: practical applications of DFM
table of contents
Pages: 69 - 72
Year of Publication: 2006
ISBN:1-59593-381-6
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Downloads (6 Weeks): 9, Downloads (12 Months): 128, Citation Count: 20
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ABSTRACT
In this paper, we propose a novel methodology for statistical SRAM design and analysis. It relies on an efficient form of importance sampling, mixture importance sampling. The method is comprehensive, computationally efficient and the results are in excellent agreement with those obtained via standard Monte Carlo techniques. All this comes at significant gains in speed and accuracy, with speedup of more than 100X compared to regular Monte Carlo. To the best of our knowledge, this is the first time such a methodology is applied to the analysis of SRAM designs.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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D. E. Hocevar, M. R. Lightner, and T. N. Trick, "A Study of Variance Reduction Techniques for Estimating Circuit Yields", IEEE Trans. on CAD, vol. 2, no. 3, pp. 180--192, July 1983.
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R. V. Joshi et al., "Variability analysis for Sub-100 nm PD/SOI CMOS SRAM cell", Proc. of the 30th ESSCC, 2004, pp. 211--214.
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J. A. G. Jess , K. Kalafala , S. R. Naidu , R. H. J. M. Otten , C. Visweswariah, Statistical timing for parametric yield prediction of digital integrated circuits, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
[doi> 10.1145/775832.776066]
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W. G. Cochran, Sampling Techniques, 3rd edition. New York: Wiley, 1977.
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T. C. Hesterberg, "Advances in importance sampling", Ph.D. Dissertation, Statistics Department, Stanford University, 1988.
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D.S. Gibson, R. Poddar, G. S. May, M. A. Brooke, "Statistically based parametric yield prediction for integrated circuits", IEEE Trans. on Semiconductor Manufacturing, vol. 10, no. 4, pp.445--458 Nov. 1997.
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G. Schueller, H. Pradlewarter, and P. S. Koutsourelakis, "A comparative study of reliability estimation procedures for high dimensions", 16th ASCE Engineering mechanics conference, 2003.
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A. J. Bhavnagarwala, T. Xinghai, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability", IEEE JSSC, vol. 36, no. 4, pp. 658--665, April 2001.
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CITED BY 20
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Gregory K. Chen , David Blaauw , Trevor Mudge , Dennis Sylvester , Nam Sung Kim, Yield-driven near-threshold SRAM design, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
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M. Zhang , M. Olbrich , D. Seider , M. Frerichs , H. Kinzelbach , E. Barke, CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
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Rajiv Joshi , Rouwaida Kanj , Keunwoo Kim , Richard Williams , Ching-Te Chuang, A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
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Rouwaida Kanj , Rajiv Joshi , Zhuo Li , JB Kuang , Hung Ngo , Ying Zhou , Weiping Shi , Sani Nassif, SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
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