A reconfigurable design-for-debug infrastructure for SoCs

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A reconfigurable design-for-debug infrastructure for SoCs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 43rd annual Design Automation Conference table of contents

San Francisco, CA, USA

SESSION: Session 2: special session: why doesn't my system work? table of contents

Pages: 7 - 12

Year of Publication: 2006

ISBN:1-59593-381-6

Authors

Miron Abramovici	DAFCA, Inc., Framingham, MA
Paul Bradley	DAFCA, Inc., Framingham, MA
Kumar Dwarakanath	DAFCA, Inc., Framingham, MA
Peter Levin	DAFCA, Inc., Framingham, MA
Gerard Memmi	DAFCA, Inc., Framingham, MA
Dave Miller	DAFCA, Inc., Framingham, MA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 18, Downloads (12 Months): 112, Citation Count: 12

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. Berent. Debugging Techniques for Embedded Systems using Real-Time Software Trace. http://www.arm.com/pdfs/CoresightWhitepaper.pdf
	2	J. Bower, O. Mencer, W. Luck, and M. Abramovici. An SoC with Reconfigurable Debug Infrastructure. Proceedings of COOL Chips IX Conf., April 2006
	3	Collett ASIC/IC Verification Study, 2004 (data for 180nm and 130nm)
	4	Jiang, W., T. Marwah and D. Bouldin. Enhancing Reliability and Flexibility of a System-on-Chip Using Reconfigurable Logic. Proc. of the Midwest Symp. on Circuits and Systems, Aug. 2005.
	5	Yu-Chin Hsu , Bassam Tabbara , Yirng-An Chen , Furshing Tsai, Advanced techniques for RTL debugging, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775927]
	6	Yu-Chin Hsu , Furshing Tsai , Wells Jong , Ying-Tsai Chang, Visibility enhancement for silicon debug, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146917]
	7	Noha Kafafi , Kimberly Bozman , Steven J. E. Wilton, Architectures and algorithms for synthesizable embedded programmable logic cores, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA [doi>10.1145/611817.611820]
	8	R. Leatherman, B. Ableidinger, and N. Stollon. Processor and System Bus On-Chip Instrumentation. Proc. Embedded Systems Conference, April 2003.
	9	Noha Kafafi , Kimberly Bozman , Steven J. E. Wilton, Architectures and algorithms for synthesizable embedded programmable logic cores, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA [doi>10.1145/611817.611820]
	10	Bart Vermeulen , Sandeep Kumar Goel, Design for Debug: Catching Design Errors in Digital Chips, IEEE Design & Test, v.19 n.3, p.37-45, May 2002
	11	http://www.accellera.org/activities/ovl/

CITED BY 13

	Yu-Chin Hsu , Furshing Tsai , Wells Jong , Ying-Tsai Chang, Visibility enhancement for silicon debug, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Kai-hui Chang , Igor L. Markov , Valeria Bertacco, Reap what you sow: spare cells for post-silicon metal fix, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Steven J.E. Wilton , Chun Hok Ho , Bradley Quinton , Philip H.W. Leong , Wayne Luk, A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications, ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.1 n.1, p.1-25, March 2008
	Sung-Boem Park , Subhasish Mitra, IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Ming-Chang Hsieh , Chih-Tsun Huang, An embedded infrastructure of debug and trace interface for the DSP platform, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Kai-hui Chang , Igor L. Markov , Valeria Bertacco, Automating post-silicon debugging and repair, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Ho Fai Ko , Nicola Nicolici, On automated trigger event generation in post-silicon validation, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Ho Fai Ko , Nicola Nicolici, Automated trace signals identification and state restoration for improving observability in post-silicon validation, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Shan Tang , Qiang Xu, In-band cross-trigger event transmission for transaction-based debug, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Flavio M. De Paula , Marcel Gort , Alan J. Hu , Steven J. E. Wilton , Jin Yang, BackSpace: formal analysis for post-silicon debug, Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design, p.1-10, November 17-20, 2008, Portland, Oregon
	Qunzeng Liu , Sachin S. Sapatnekar, Synthesizing a representative critical path for post-silicon delay prediction, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA
	Miron Abramovici , Paul Bradley, Integrated circuit security: new threats and solutions, Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies, April 13-15, 2009, Oak Ridge, Tennessee
	Ho Fai Ko , Nicola Nicolici, Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.2, p.285-297, February 2009