| Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor |
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Language, Compiler and Tool Support for Embedded Systems
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Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
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Ottawa, Ontario, Canada
SESSION: Low power issues
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Pages: 153 - 162
Year of Publication: 2006
ISBN:1-59593-362-X
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Downloads (6 Weeks): 1, Downloads (12 Months): 53, Citation Count: 5
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ABSTRACT
As the dynamic voltage scaling (DVS) technique provides system engineers the flexibility to trade-off the performance and the energy consumption, DVS has been adopted in many computing systems. However, the longer a job executes, the more energy in the leakage current the device/processor consumes for the job. To reduce the energy consumption resulting from the leakage current, a system might enter the dormant mode. This paper targets energy-efficient rate-monotonic scheduling for periodic real-time tasks on a uniprocessor DVS system with non-negligible leakage power consumption. An on-line simulated scheduling strategy and a virtually blocking time strategy are developed for procrastination scheduling to reduce energy consumption. The proposed algorithms derive a feasible schedule for real-time tasks with worst-case guarantees for any input instance. Experimental results show that our proposed algorithms could derive energy-efficient solutions.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 5
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Jian-Jia Chen , Tei-Wei Kuo , Chia-Lin Yang , Ku-Jei King, Energy-efficient real-time task scheduling with task rejection, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
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Jaw-Wei Chi , Chia-Lin Yang , Yi-Jung Chen , Jien-Jia Chen, Cache leakage control mechanism for hard real-time systems, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
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