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Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor
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Source Language, Compiler and Tool Support for Embedded Systems archive
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems table of contents
Ottawa, Ontario, Canada
SESSION: Low power issues table of contents
Pages: 153 - 162  
Year of Publication: 2006
ISBN:1-59593-362-X
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Authors
Jian-Jia Chen  National Taiwan University, Taiwan
Tei-Wei Kuo  National Taiwan University, Taiwan
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
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ABSTRACT

As the dynamic voltage scaling (DVS) technique provides system engineers the flexibility to trade-off the performance and the energy consumption, DVS has been adopted in many computing systems. However, the longer a job executes, the more energy in the leakage current the device/processor consumes for the job. To reduce the energy consumption resulting from the leakage current, a system might enter the dormant mode. This paper targets energy-efficient rate-monotonic scheduling for periodic real-time tasks on a uniprocessor DVS system with non-negligible leakage power consumption. An on-line simulated scheduling strategy and a virtually blocking time strategy are developed for procrastination scheduling to reduce energy consumption. The proposed algorithms derive a feasible schedule for real-time tasks with worst-case guarantees for any input instance. Experimental results show that our proposed algorithms could derive energy-efficient solutions.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Jian-Jia Chen: colleagues
Tei-Wei Kuo: colleagues