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Compiler and runtime support for efficient software transactional memory
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Source Conference on Programming Language Design and Implementation archive
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation table of contents
Ottawa, Ontario, Canada
SESSION: Transactions table of contents
Pages: 26 - 37  
Year of Publication: 2006
ISBN:1-59593-320-4
Also published in ...
Authors
Ali-Reza Adl-Tabatabai  Intel Labs, Santa Clara, CA
Brian T. Lewis  Intel Labs, Santa Clara, CA
Vijay Menon  Intel Labs, Santa Clara, CA
Brian R. Murphy  Intel China Research Center, Beijing, China
Bratin Saha  Intel Labs, Santa Clara, CA
Tatiana Shpeisman  Intel Labs, Santa Clara, CA
Sponsors
ACM: Association for Computing Machinery
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 27,   Downloads (12 Months): 373,   Citation Count: 58
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ABSTRACT

Programmers have traditionally used locks to synchronize concurrent access to shared data. Lock-based synchronization, however, has well-known pitfalls: using locks for fine-grain synchronization and composing code that already uses locks are both difficult and prone to deadlock. Transactional memory provides an alternate concurrency control mechanism that avoids these pitfalls and significantly eases concurrent programming. Transactional memory language constructs have recently been proposed as extensions to existing languages or included in new concurrent language specifications, opening the door for new compiler optimizations that target the overheads of transactional memory.This paper presents compiler and runtime optimizations for transactional memory language constructs. We present a high-performance software transactional memory system (STM) integrated into a managed runtime environment. Our system efficiently implements nested transactions that support both composition of transactions and partial roll back. Our JIT compiler is the first to optimize the overheads of STM, and we show novel techniques for enabling JIT optimizations on STM operations. We measure the performance of our optimizations on a 16-way SMP running multi-threaded transactional workloads. Our results show that these techniques enable transactional memory's performance to compete with that of well-tuned synchronization.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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CITED BY  58

Collaborative Colleagues:
Ali-Reza Adl-Tabatabai: colleagues
Brian T. Lewis: colleagues
Vijay Menon: colleagues
Brian R. Murphy: colleagues
Bratin Saha: colleagues
Tatiana Shpeisman: colleagues