Reducing dynamic and leakage energy in VLIW architectures

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Reducing dynamic and leakage energy in VLIW architectures

Full text

Pdf (1.20 MB)

Source

ACM Transactions on Embedded Computing Systems (TECS) archive
Volume 5 , Issue 1 (February 2006) table of contents

Pages: 1 - 28

Year of Publication: 2006

ISSN:1539-9087

Authors

W. Zhang	Pennsylvania State University, University Park, PA
Y.-F. Tsai	Pennsylvania State University, University Park, PA
D. Duarte	Pennsylvania State University, University Park, PA
N. Vijaykrishnan	Pennsylvania State University, University Park, PA
M. Kandemir	Pennsylvania State University, University Park, PA
M. J. Irwin	Pennsylvania State University, University Park, PA

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 15, Downloads (12 Months): 79, Citation Count: 0

Additional Information:

abstract references index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1132357.1132358 What is a DOI?

ABSTRACT

The mobile computing device market has been growing rapidly. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in the future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule slacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present three compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. Integer ALU (IALU) components operating with multiple supply voltages are designed to provide different low-energy versions that possess different operational latencies. The goal of the first technique explored is to maximize the number of operations mapped to IALU components with the lowest energy consumption without extending the schedule length. We also consider a variant of this technique that saves more energy at the cost of some performance loss. The second technique uses two leakage-control mechanisms to reduce leakage energy consumption when no operations are scheduled in the component. Our evaluation of these two approaches, using fifteen benchmarks, shows that based on the number and duration of slacks, the availability of low-energy functional units and the relative magnitude of leakage and dynamic energy, either leakage or dynamic energy consumption, will provide more energy gains. Finally, we provide a unified energy-optimization strategy that integrates both dynamic and leakage energy-reduction schemes. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit-level simulation. Our results show that the unified scheme generates better results than using either of dynamic and leakage energy-reduction techniques independently.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Anand , M. Jacome , G. de Veciana, Heuristic tradeoffs between latency and energy consumption in register assignment, Proceedings of the eighth international workshop on Hardware/software codesign, p.115-119, May 2000, San Diego, California, United States [doi>10.1145/334012.334034]
	2	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000 [doi>10.1145/335043.335044]
	3	Shekhar Borkar, Design Challenges of Technology Scaling, IEEE Micro, v.19 n.4, p.23-29, July 1999 [doi>10.1109/40.782564]
	4	J. Adam Butts , Gurindar S. Sohi, A static power model for architects, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.191-201, December 2000, Monterey, California, United States [doi>10.1145/360128.360148]
	5	Casmira, J. and Grunwald, D. 2000. Dynamic instruction scheduling slack. In 2000 Kool Chips Workshop.
	6	Francky Catthoor , Eddy de Greef , Sven Suytack, Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design, Kluwer Academic Publishers, Norwell, MA, 1998
	7	Anantha P. Chandrakasan , Robert W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, Norwell, MA, 1995
	8	Anantha P. Chandrakasan , William J. Bowhill , Frank Fox, Design of High-Performance Microprocessor Circuits, Wiley-IEEE Press, 2000
	9	Jui-Ming Chang , Massoud Pedram, Energy minimization using multiple supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.436-443, Dec. 1997 [doi>10.1109/92.645070]
	10	G. Chen , R. Shetty , M. Kandemir , N. Vijaykrishnan , M. J. Irwin , M. Wolczko, Tuning Garbage Collection in an Embedded Java Environment, Proceedings of the 8th International Symposium on High-Performance Computer Architecture, p.92, February 02-06, 2002
	11	and M. J. Irwin, DRAM Energy Management Using Sof ware and Hardware Directed Power Mode Control, Proceedings of the 7th International Symposium on High-Performance Computer Architecture, p.159, January 20-24, 2001
	12	David Duarte , Yuh-Fang Tsai , Narayanan Vijaykrishnan , Mary Jane Irwin, Evaluating Run-Time Techniques for Leakage Power Reduction, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.31, January 07-11, 2002
	13	V. M. Goulart Ferreira , H. Yasuura, Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-Offs, Proceedings of the 13th symposium on Integrated circuits and systems design, p.165, September 18-24, 2000
	14	Halter, J. P. and Najm, F. 1997. A gate-level leakage power reduction method for ultra-low-power cmos circuits. In IEEE Custom Integrated Circuits Conference. 475--478.
	15	Wen-Mei W. Hwu , Scott A. Mahlke , William Y. Chen , Pohua P. Chang , Nancy J. Warter , Roger A. Bringmann , Roland G. Ouellette , Richard E. Hank , Tokuzo Kiyohara , Grant E. Haab , John G. Holm , Daniel M. Lavery, The superblock: an effective technique for VLIW and superscalar compilation, The Journal of Supercomputing, v.7 n.1-2, p.229-248, May 1993 [doi>10.1007/BF01205185]
	16	Johnson, M., Somasekhar, D., and Roy, K. 1999. Models and algorithms for bounds in cmos circuits. IEEE Transactions on CAD of Integrated Circuits and Systems 18, 6 (June). 714--725.
	17	Stefanos Kaxiras , Zhigang Hu , Margaret Martonosi, Cache decay: exploiting generational behavior to reduce cache leakage power, Proceedings of the 28th annual international symposium on Computer architecture, p.240-251, June 30-July 04, 2001, Göteborg, Sweden
	18	Kim, H. Y., Vijaykrishnan, N., Kandemir, M., and Irwin, M. J. 2001. A framework for exploring energy-efficient vliw architectures. In International Conference on Computer Design.
	19	Klaiber, A. 2000. The technology behind crusoe processors. Whitepaper, Transmeta Corporation.
	20	Tadahiro Kuroda , Takayasu Sakurai, Threshold-voltage control schemes through substrate-bias for low-power high-speed CMOS LSI design, Journal of VLSI Signal Processing Systems, v.13 n.2-3, p.191-201, Aug./Sept. 1996 [doi>10.1007/BF01130405]
	21	Alvin R. Lebeck , Xiaobo Fan , Heng Zeng , Carla Ellis, Power aware page allocation, Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, p.105-116, November 2000, Cambridge, Massachusetts, United States
	22	Weiping Liao , Lei He, Power modeling and reduction of VLIW processors, Compilers and operating systems for low power, Kluwer Academic Publishers, Norwell, MA, 2003
	23	Yung-Hsiang Lu , Luca Benini , Giovanni De Micheli, Operating-system directed power reduction, Proceedings of the 2000 international symposium on Low power electronics and design, p.37-42, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344189]
	24	Scott A. Mahlke , David C. Lin , William Y. Chen , Richard E. Hank , Roger A. Bringmann, Effective compiler support for predicated execution using the hyperblock, Proceedings of the 25th annual international symposium on Microarchitecture, p.45-54, December 01-04, 1992, Portland, Oregon, United States
	25	K. Masselos , C. E. Goutis , F. Catthoor , H. DeMan, Interaction between Sub-word Parallelism Exploitation and Low Power Code Transformations for VLIW Multi-media Processors, Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, p.52, March 04-05, 1999
	26	Steven S. Muchnick, Advanced compiler design and implementation, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1998
	27	Nagendra, C., Irwin, M. J., and Owens, R. M. 1996. Area-time-power tradeoffs in parallel adders. IEEE Transactions on Circuits and Systems II 43, 10 (Oct.), 689--702.
	28	Takanori Okuma , Tohru Ishihara , Hiroto Yasuura, Real-Time Task Scheduling for a Variable Voltage Processor, Proceedings of the 12th international symposium on System synthesis, p.24, November 01-04, 1999
	29	Salil Raje , Majid Sarrafzadeh, Variable voltage scheduling, Proceedings of the 1995 international symposium on Low power design, p.9-14, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224084]
	30	Roy, K. and Prasad, S. C. 2000. Low-Power CMOS VLSI Circuit Design. Wiley Interscience, NY.
	31	Mariagiovanna Sami , Donatella Sciuto , Cristina Silvano , Vittorio Zaccaria, Power exploration for embedded VLIW architectures, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	32	M. Sami , D. Sciuto , C. Silvano , V. Zaccaria , R. Zafalon, Exploiting data forwarding to reduce the power budget of VLIW embedded processors, Proceedings of the conference on Design, automation and test in Europe, p.252-257, March 2001, Munich, Germany
	33	D. Shin , J. Kim , N. Chang, An operation rearrangement technique for power optimization in VLIM instruction fetch, Proceedings of the conference on Design, automation and test in Europe, p.809, March 2001, Munich, Germany
	34	Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Jingyan Zuo , Abhijit Dharchoudhury , Rajendran Panda , David Blaauw, Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing, Proceedings of the 36th ACM/IEEE conference on Design automation, p.436-441, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309975]
	35	Toburen, M. C., Conte, T. M., and Reilly, M. 1998. Instruction scheduling for low power dissipation in high performance processors. In Power Driven Microarchitecture Workshop.
	36	Trimaran home page. http://www.trimaran.org.
	37	Se-Hyun Yang , Babak Falsafi , Michael D. Powell , Kaushik Roy , T. N. Vijaykumar, An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches, Proceedings of the 7th International Symposium on High-Performance Computer Architecture, p.147, January 20-24, 2001
	38	Ye, Y., Borkar, S., and De, V. 1998. A new technique for standby leakage reduction in high-performance circuits. In Symposium on VLSI Circuits,. 40--41.
	39	Han-Saem Yun , Jihong Kim, Power-aware modulo scheduling for high-performance VLIW processors, Proceedings of the 2001 international symposium on Low power electronics and design, p.40-45, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383091]