Vulnerability analysis of L2 cache elements to single event upsets

ABSTRACT

Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the probability of particle strikes in these elements is high and can significantly impact overall processor reliability. Previous work [2] has developed effective metrics to accurately measure the vulnerability of cache memory elements. Based on these metrics, we have developed a reliability-performance evaluation framework, which has been built upon the Simplescalar simulator.In this work, we focus on the reliability aspects of L1 and L2 caches. Specifically, we present algorithms for tag vulnerability computation and investigate and report in detail on the vulnerability of data, tag, and status bits in the L2 array. Experiments on SPECint2K and SPECfp2K benchmarks show that one class of error, replacement error, makes up almost 85% of the total tag vulnerability of a 1MB write-back L2 cache. In addition, the vulnerability of L2 tag-addresses significantly increases as the size of the memory address space increases. Results show that the L2 tag array can be as susceptible as first-level instruction and data caches (IL1/DL1) to soft errors.

REFERENCES

• 1: AMD Athlon(TM) 64 Processor, http://www.amd.com.
• 2: H. Asadi, V. Sridharan, M. B. Tahoori, D. Kaeli, "Balancing Performance and Reliability in the Memory Hierarchy," Proc. of the IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS), Austin, Texas, March 2005.
• 3: S. Behling, R. Bell, P. Farrell, H. Holthoff, F. O. Connell, and W. Weir, "The POWER4 Processor Introduction and Tuning Guide," IBM redbooks, www.redbooks.ibm.com. Nov. 2001.
• 4: Arijit Biswas , Paul Racunas , Razvan Cheveresan , Joel Emer , Shubhendu S. Mukherjee , Ram Rangan, Computing Architectural Vulnerability Factors for Address-Based Structures, Proceedings of the 32nd Annual International Symposium on Computer Architecture, p.532-543, June 04-08, 2005
• 5: D. Burger and T. M. Austin, "The SimpleScalar Tool Set, Version 2.0," University of Wisconsin-Madison, Computer Science Dept., Technical Report No. 1342, June 1997.
• 6: Jiri Gaisler, Evaluation of a 32-bit Microprocessor with Built-In Concurrent Error-Detection, Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97), p.42, June 25-27, 1997
• 7: S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walstra, and C. Dai, "Impact of CMOS Scaling and SOI on Soft Error Rates of Logic Processes," Symp. on VLSI Technology, Digest of Tech. Papers, pp. 73--74, June 2001.
• 8: Intel Pentium IV Processor, http://www.intel.com.
• 9: Barry W. Johnson, Design & analysis of fault tolerant digital systems, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1988
• 10: R. Kalla, S. Balaram, J. M Tendler, "IBM Power5 Chip: a Dual-Core Multi-threaded Processor," IEEE Micro, pp. 40--47, Vol. 24, Issue 2, Mar-Apr 2004.
• 11: R. E. Kessler, The Alpha 21264 Microprocessor, IEEE Micro, v.19 n.2, p.24-36, March 1999 [doi>10.1109/40.755465]
• 12: Seongwoo Kim , Arun K. Somani, Area efficient architectures for information integrity in cache memories, Proceedings of the 26th annual international symposium on Computer architecture, p.246-255, May 01-04, 1999, Atlanta, Georgia, United States
• 13: Kevin M. Lepak , Mikko H. Lipasti, Silent stores for free, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.22-31, December 2000, Monterey, California, United States [doi>10.1145/360128.360133]
• 14: Subhasish Mitra , Norbert Seifert , Ming Zhang , Quan Shi , Kee Sup Kim, Robust System Design with Built-In Soft-Error Resilience, Computer, v.38 n.2, p.43-52, February 2005 [doi>10.1109/MC.2005.70]
• 15: Shubhendu S. Mukherjee , Christopher Weaver , Joel Emer , Steven K. Reinhardt , Todd Austin, A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.29, December 03-05, 2003
• 16: H. T. Nguyen and Y. Yagil, "A Systematic Approach to SER Estimation and Solutions," Proc. of the Intl. Reliability Physical Symp., pp. 60--70, Texas, 2003.
• 17: E. Normand, "Single Event Upset at Ground Level," IEEE Trans. on Nuclear Science, Vol. 43, No. 6, pp. 2742--2750, Dec. 1996.
• 18: Erez Perelman , Greg Hamerly , Brad Calder, Picking Statistically Valid and Early Simulation Points, Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, p.244, September 27-October 01, 2003
• 19: S. Rusu, H. Muljono, and B. Cherkauer, "Itanium 2 processor 6M: higher frequency and larger L3 cache," IEEE Micro, pp. 10--18, Vol. 24, Issue 2, Mar-Apr 2004.
• 20: T. J. Siegel , E. Pfeffer , J. A. Magee, The IBM eServer z990 microprocessor, IBM Journal of Research and Development, v.48 n.3-4, p.295-309, May 2004
• 21: SPEC CPU2000 Benchmarks, http://www.specbench.org/osg/cpu2000.
• 22: Y. Tosaka, S. Satoh, K. Suzuki, T. Suguii, H. Ehara, G. A. Woffinden, and, S. A. Wender, "Impact of Cosmic Ray Neutron Induced Soft Errors on Advanced Submicron CMOS circuits," Symposium on VLSI Technology, Digest of Technical Papers, pp. 148--149, 1996.
• 23: Christopher Weaver , Joel Emer , Shubhendu S. Mukherjee , Steven K. Reinhardt, Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor, Proceedings of the 31st annual international symposium on Computer architecture, p.264, June 19-23, 2004, München, Germany
• 24: D. Wendell, et. al., "A 4MB On-Chip L2 Cache for a 90nm 1.6GHz 64b SPARC Microprocessor," Proc. of IEEE Intl. Solid-State Circuits Conference (ISSCC), {Digest of Technical Papers}, Feb. 2004.
• 25: W. Zhang, S. Gurumurthi, M. Kandemir, and A. Siavasubramaniam, "ICR: In-Cache Replication for Enhancing Data Cache Reliability," Proc. of the Intl. Conference on Dependable Systems and Networks (DSN), pp. 291--300, June 2003.
• 26: J. F. Ziegler, Terrestrial cosmic rays, IBM Journal of Research and Development, v.40 n.1, p.19-39, Jan. 1996