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Automatic generation of operation tables for fast exploration of bypasses in embedded processors
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe: Proceedings table of contents
Munich, Germany
SESSION: Architectural level synthesis table of contents
Pages: 1197 - 1202  
Year of Publication: 2006
ISBN:3-9810801-0-6
Authors
Sanghyun Park  SO&R Labs, SNU Seoul, South Korea
Eugene Earlie  Strategic CAD Labs, Intel Corporation, Hudson, MA
Aviral Shrivastava  School of ICS, UC Irvine, CA
Alex Nicolau  School of ICS, UC Irvine, CA
Nikil Dutt  School of ICS, UC Irvine, CA
Yunheung Paek  SO&R Labs, SNU Seoul, South Korea
Sponsors
: The EDA Consortium
EDAA : European Design and Automation Association
IEEE-CS\DATC : The IEEE Computer Society
Publisher
European Design and Automation Association  3001 Leuven, Belgium, Belgium
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ABSTRACT

Customizing the bypasses in an embedded processor uncovers valuable trade-offs between the power, performance and the cost of the processor. Meaningful exploration of bypasses requires bypass-sensitive compiler. Operation Tables (OTs) have been proposed to perform bypass-sensitive compilation. However, due to lack of automated methods to generate OTs, OTs are currently manually specified by the designer. Manual specification of OTs is not only an extremely time consuming task, but is also highly error-prone. In this paper, we present AutoOT, an algorithm to automatically generate OTs from a high-level processor description. Our experiments on the Intel XScale processor model running MiBench benchmarks demonstrate that AutoOT greatly reduces the time and effort of specification. Automatic generation of OTs makes it feasible to perform full bypass exploration on the Intel XScale and thus discover interesting alternate bypass configurations in a reasonable time. To further reduce the compile-time overhead of OT generation, we propose another novel algorithm, AutoOTDB. AutoOTDB is able to cut the compile-time overhead of OT generation by half.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Sanghyun Park: colleagues
Eugene Earlie: colleagues
Aviral Shrivastava: colleagues
Alex Nicolau: colleagues
Nikil Dutt: colleagues
Yunheung Paek: colleagues