| Automatic generation of operation tables for fast exploration of bypasses in embedded processors |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Munich, Germany
SESSION: Architectural level synthesis
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Pages: 1197 - 1202
Year of Publication: 2006
ISBN:3-9810801-0-6
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Authors
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Sanghyun Park
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SO&R Labs, SNU Seoul, South Korea
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Eugene Earlie
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Strategic CAD Labs, Intel Corporation, Hudson, MA
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Aviral Shrivastava
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School of ICS, UC Irvine, CA
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Alex Nicolau
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School of ICS, UC Irvine, CA
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Nikil Dutt
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School of ICS, UC Irvine, CA
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Yunheung Paek
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SO&R Labs, SNU Seoul, South Korea
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European Design and Automation Association
3001 Leuven, Belgium, Belgium
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Downloads (6 Weeks): 2, Downloads (12 Months): 18, Citation Count: 3
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ABSTRACT
Customizing the bypasses in an embedded processor uncovers valuable trade-offs between the power, performance and the cost of the processor. Meaningful exploration of bypasses requires bypass-sensitive compiler. Operation Tables (OTs) have been proposed to perform bypass-sensitive compilation. However, due to lack of automated methods to generate OTs, OTs are currently manually specified by the designer. Manual specification of OTs is not only an extremely time consuming task, but is also highly error-prone. In this paper, we present AutoOT, an algorithm to automatically generate OTs from a high-level processor description. Our experiments on the Intel XScale processor model running MiBench benchmarks demonstrate that AutoOT greatly reduces the time and effort of specification. Automatic generation of OTs makes it feasible to perform full bypass exploration on the Intel XScale and thus discover interesting alternate bypass configurations in a reasonable time. To further reduce the compile-time overhead of OT generation, we propose another novel algorithm, AutoOTDB. AutoOTDB is able to cut the compile-time overhead of OT generation by half.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 3
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Florian Brandner , Dietmar Ebner , Andreas Krall, Compiler generation from structural architecture descriptions, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
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