Layout driven data communication optimization for high level synthesis

ABSTRACT

High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the final circuit layout. In this paper, we present a physically aware design flow for mapping high level application specifications to a synthesizable register transfer level hardware description. We study the problem of optimizing the data communication of the variables in the application specification. Our algorithm uses floorplan information that guides the optimization. We develop a simple, yet effective, incremental floorplanner to handle the perturbations caused by the data communication optimization. We show that the proposed techniques can reduce the wirelength of the final design, while maintaining a legal floorplan with the same area as the initial floorplan.

REFERENCES

• 1: Adam Kaplan , Philip Brisk , Ryan Kastner, Data communication estimation and reduction for reconfigurable systems, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775987]
• 2: R. Cytron , J. Ferrante , B. K. Rosen , M. N. Wegman , F. K. Zadeck, An efficient method of computing static single assignment form, Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.25-35, January 11-13, 1989, Austin, Texas, United States [doi>10.1145/75277.75280]
• 3: Mihai Budiu , Seth Copen Goldstein, Compiling Application-Specific Hardware, Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications, p.853-863, September 02-04, 2002
• 4: Justin L. Tripp , Preston A. Jackson , Brad Hutchings, Sea Cucumber: A Synthesizing Compiler for FPGAs, Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications, p.875-885, September 02-04, 2002
• 5: W. Gong, G. Wang, and R. Kastner, "A High Performance Intermediate Representation for Reconfigurable Systems," International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004.
• 6: Pradeep Prabhakaran , Prithviraj Banerjee, Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis, Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing, p.428, January 04-07, 1998
• 7: Yung-Ming Fang , D. F. Wong, Simultaneous functional-unit binding and floorplanning, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.317-321, November 06-10, 1994, San Jose, California, United States
• 8: William E. Dougherty , Donald E. Thomas, Unifying behavioral synthesis and physical design, Proceedings of the 37th conference on Design automation, p.756-761, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337769]
• 9: D. W. Knapp, "Fasolt: a program for feedback-driven datapath optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 11, pp. 677--95, 1992.
• 10: S. Tarafdar and M. Leeser, "A data-centric approach to high-level synthesis," IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 19, pp. 1251--67, 2000.
• 11: Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 12: A. Ranjan, and M. Sarrafzadeh, "Floorplanner 1000 Times Faster: A Good Predictor and Constructor," Workshop on System-Level Interconnection Prediction (SLIP), 1999.