Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults

ABSTRACT

We present a very effective on-line interconnect built-in-self-test (BIST) method I-BIST for FPGAs that uses a combination of the following novel techniques: a track-adjacent and a switch-adjacent (also called "mirror adjacent") pairwise net comparison mechanism that achieves high detectability, a carefully designed set of only five net-configurations that cover all types and locations of wire-segment and switch faults, a 2-phase global-detailed testing approach, and a divide-and-conquer technique used in detailed testing to quickly narrow down the set of potential suspect interconnects that are then detail-diagnosed. These techniques result in I-BIST having provable detectability in the presence of an unbounded number of multiple faults, very high diagnosability of 99-100% even for high fault densities of up to 10% that are expected in emerging nano-scale technologies, and much lower test times or fault latencies than the previous best interconnect BIST techniques. In particular, for application to on-line testing, our method re- quires 2n roving-tester (ROTE) configurations to test an entire n x n FPGA, while the previous best online interconnect BIST technique re- quires n² configurations. Thus, I-BIST is an order of magnitude more time- as well as power-efficient, and will scale well with rapidly increas- ing FPGA device sizes that are expected in emerging technologies.

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