Parallel co-simulation using virtual synchronization with redundant host execution

ABSTRACT

In traditional parallel co-simulation approaches, the simulation speed is heavily limited by time synchronization overhead between simulators and idle time caused by data dependency. Recent work has shown that the time synchronization overhead can be reduced significantly by predicting the next synchronization points more effectively or by separating trace-driven architecture simulation from trace generation from component simulators. The latter is known as virtual synchronization technique. In this paper, we propose redundant host execution to minimize the simulation idle time caused by data dependency in simulation models. By combining virtual synchronization and redundant host execution techniques we could make parallel execution of multiple simulators a viable solution for fast but cycle-accurate co-simulation. Experiments show about 40% performance gain over a technique which uses virtual synchronization only.

REFERENCES

• 1: J. Jung , S. Yoo , K. Choi, Performance improvement of multi-processor systems cosimulation based on SW analysis, Proceedings of the conference on Design, automation and test in Europe, p.749-753, March 2001, Munich, Germany
• 2: Dohyung Kim , Youngmin Yi , Soonhoi Ha, Trace-driven HW/SW cosimulation using virtual synchronization technique, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA [doi>10.1145/1065579.1065669]
• 3: David Nicol , Philip Heidelberger, Parallel execution for serial simulators, ACM Transactions on Modeling and Computer Simulation (TOMACS), v.6 n.3, p.210-242, July 1996 [doi>10.1145/235025.235031]
• 4: Richard M. Fujimoto, Parallel discrete event simulation, Communications of the ACM, v.33 n.10, p.30-53, Oct. 1990 [doi>10.1145/84537.84545]
• 5: N. Manjikian, "Parallel Simulation of Multiprocessor Execution: Implementation and Results for SimpleScalar," Proceedings of the 2001 IEEE Symposium on Performance Analysis of Systems and Software, Arizona, Nov. 4--6, 2001, pp. 147--151.
• 6: Shubhendu S. Mukherjee , Steven K. Reinhardt , Babak Falsafi , Mike Litzkow , Mark D. Hill , David A. Wood , Steven Huss-Lederman , James R. Larus, Wisconsin Wind Tunnel II: A Fast, Portable Parallel Architecture Simulator, IEEE Concurrency, v.8 n.4, p.12-20, October 2000 [doi>10.1109/4434.895100]
• 7: Sungjoo Yoo , Kiyoung Choi, Optimistic distributed timed cosimulation based on thread simulation model, Proceedings of the 6th international workshop on Hardware/software codesign, p.71-75, March 15-18, 1998, Seattle, Washington, United States
• 8: D. Kim, C. Rhee, and S. Ha, "Combined Data-driven and Event-driven Scheduling Technique for Fast Distributed Co-simulation", IEEE Transactions on Very large Scale Integration Systems Vol. 10 pp 672--679 Oct. 2002
• 9: Guang Yang , Alberto Sangiovanni-Vincentelli , Yosinori Watanabe , Felice Balarin, Separation of concerns: overhead in modeling and efficient simulation techniques, Proceedings of the 4th ACM international conference on Embedded software, September 27-29, 2004, Pisa, Italy [doi>10.1145/1017753.1017765]
• 10: Andy D. Pimentel , Louis O. Hertzberger , Paul Lieverse , Pieter van der Wolf , Ed F. Deprettere, Exploring Embedded-Systems Architectures with Artemis, Computer, v.34 n.11, p.57-63, November 2001 [doi>10.1109/2.963445]
• 11: D. Burger and T. Austin, "The SimpleScalar Toolset, Version 2.0," University of Wisconsin-Madison Computer Sciences Department Technical Report #1342, June 1997.
• 12: Shaojie Wang , Sharad Malik , Reinaldo A. Bergamaschi, Modeling and Integration of Peripheral Devices in Embedded Systems, Proceedings of the conference on Design, Automation and Test in Europe, p.10136, March 03-07, 2003
• 13: http://peace.snu.ac.kr/research/peace/