Analyzing timing uncertainty in mesh-based clock architectures

ABSTRACT

Mesh architectures are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations between signal nodes spatially distributed over the chip. However, one problem with the mesh architectures is the difficulty in accurately analyzing large instances. Furthermore, variations in process and temperature, supply noise and crosstalk noise cause uncertainty in the delay from clock source to flip-flops. In this paper, we study the problem of analyzing timing uncertainty in mesh-based clock architectures. We propose solutions for both pure mesh and (mesh + global-tree) architectures. The solutions can handle large design and mesh instances. The maximum error in uncertainty values reported by our solutions is 1-3ps with respect to the golden Monte Carlo simulations, which is at most 0.5% of the nominal clock latency of about 600ps.

REFERENCES

• 1: A. Agarwal, V. Zolotov, and D. T. Blaauw. Statistical Clock Skew Analysis Considering Intra-die Process Variations. In IEEE Trans. on CAD, pages 1231--1242, August 2004.
• 2: D. W. Bailey and B. J. Benscheneider. Clocking Design and Analysis for a 600-MHz Alpha Microprocessor. In IEEE JSSC Vol 33., No. 11, pages 1627--1633, November 1998.
• 3: K. A. Bowman, S. G. Duvall, and J. D. Meindl. Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration. In IEEE JSSC, pages 183--190, February 2002.
• 4: H. Chen , C. Yeh , G. Wilke , S. Reddy , H. Nguyen , W. Walker , R. Murgai, A sliding window scheme for accurate clock mesh analysis, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.939-946, November 06-10, 2005, San Jose, CA
• 5: P. J. Camporese et al., X-Y Grid Tree Tuning Method. In U.S. Patent, No. 6,205,571 B1, March 2001.
• 6: G. Northrop et. al. A 600-MHz G5 S/390 Microprocessor. In ISSCC Tech. Dig., pages 88--89, February 1999.
• 7: Robert B. Hitchcock, Sr., Timing Verification and the Timing Analysis program, Proceedings of the 19th conference on Design automation, p.594-604, January 1982
• 8: Ying Liu , Sani R. Nassif , Lawrence T. Pileggi , Andrzej J. Strojwas, Impact of interconnect variations on the clock skew of a gigahertz microprocessor, Proceedings of the 37th conference on Design automation, p.168-171, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337365]
• 9: M. Berkelaar. Statistical Delay Calculation, A Linear Time Method. In TAU, pages 15--24, December 1997.
• 10: Michael Orshansky , Linda Milor , Pinhong Chen , Kurt Keutzer , Chenming Hu, Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 11: L. T. Pillage and R. A. Rohrer. Asymptotic Waveform Evaluation for Timing Analysis. In IEEE Transactions on Computer-Aided Design, pages 352--366, April 1990.
• 12: P. J. Restle et. al. A Clock Distribution Network for Microprocessor. In IEEE JSSC Vol 36., No. 5, May 2001.
• 13: R. Heald et. al. Implementation of a 3rd-Generation SPARC V9 64b Microprocessor. In ISSCC Dig. Tech. Papers, pages 412--413, February 2000.
• 14: S. B. Samaan, The impact of device parameter variations on the frequency and performance of VLSI chips, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.343-346, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382598]
• 15: C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996663]
• 16: Gustavo Wilke and Rajeev Murgai. Accuracy of Interconnect Pi Models. In Fujitsu Laboratories of America Internal Document, August 2004.
• 17: S. Zanella, A. Nardi, A. Neviani, M. Quarantelli, S. Saxena, and C. Guardiani. Analysis of the Impact of Process Variations on Clock Skew. In IEEE Trans. on Semiconductor Manufacturing, pages 401--407, November 2000.
• 18: P. S. Zuchowski , P. A. Habitz , J. D. Hayes , J. H. Oppold, Process and environmental variation impacts on ASIC timing, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.336-342, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382597]