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ABSTRACT

Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performance. One reason is that tasks can run in parallel but configurations of the tasks can be done only in sequence. This work presents a novel configuration model to enable configuration parallelism. It consists of multiple homogeneous tiles and each tile has its own configuration SRAM that can be individually accessed. Thus multiple configuration controllers can load tasks in parallel and more speedups can be achieved. We used a prefetch scheduling technique to evaluate the model with randomly generated tasks. The experiment results reveal that in average using multiple controllers can reduce the configuration overheads by 21%. Compared to best cases of using multiple tiles with a single controller, additional 40% speedup can be achieved using multiple controllers.

REFERENCES

• 1: Hartej Singh , Ming-Hau Lee , Guangming Lu , Nader Bagherzadeh , Fadi J. Kurdahi , Eliseu M. Chaves Filho, MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications, IEEE Transactions on Computers, v.49 n.5, p.465-481, May 2000 [doi>10.1109/12.859540]
• 2: Scott Hauck, Configuration prefetch for single context reconfigurable coprocessors, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.65-74, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275121]
• 3: Y. Qu, et al, "Using multiple configuration controllers to reduce the configuration overhead", IEEE Proceedings of the 23rd Norchip conference, pp. 86--89, 2005.
• 4: Javier Resano , Daniel Mozos , Francky Catthoor, A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware, Proceedings of the conference on Design, Automation and Test in Europe, p.106-111, March 07-11, 2005 [doi>10.1109/DATE.2005.18]
• 5: Li Shang , Niraj K. Jha, Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.345, January 07-11, 2002
• 6: Xilinx, datasheet and application notes, www.xilinx.com.
• 7: O. Diessel, et. al, "Dynamic scheduling of tasks on partially reconfigurable FPGAs", IEE Proc.-Comput. Digit Tech, Vol. 147, No. 3, pp. 181--188, 2000.
• 8: PACT XPP Technologies, "Reconfiguration White Paper", www.pactcorp.com.