Extraction of defect density and size distributions from wafer sort test results

ABSTRACT

Defect density and defect size distributions (DDSDs) are key parameters used in IC yield loss predictions. Traditionally, memories and specialized test structures have been used to estimate these distributions. In this paper, we propose a strategy to accurately estimate DDSDs for shorts in metal layers using production IC test results.

REFERENCES

• 1: J. Kibarian, "The nature of yield ramping: Keeping ahead of evolution," International Test Conference, Keynote Address, 2005.
• 2: Young-Jun Kwon , D. M. H. Walker, Yiel Learning via Functional Test Data, Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test, p.626-635, October 21-25, 1995
• 3: W. Maly, "Spot Defect Size Measurements Using Results of Functional Test for Yield Loss Modeling of VLSI IC," White Paper, CMU, Sep. 2004.
• 4: J. E. Nelson, T. Zanon, R. Desineni, J. G. Brown, N. Patil, W. Maly, and R. D. Blanton, "Extraction of Defect Densities and Size Distributions from Wafer Probe Test Results," CSSI Technology Report #05-02, Carnegie Mellon University, Feb 2005.
• 5: J. Khare, D. Feltham and W. Maly, "Accurate Estimation of Defect-Related Yield Loss in Reconfigurable VLSI Circuits," IEEE Journal of Solid State Circuits, vol. 8, no. 2, pp. 146--156, Feb. 1993.
• 6: W. Maly and J. Deszczka, "Yield Estimation Model for VLSI Artwork Evaluation," Electronic Letters, vol. 19, no. 6, pp. 226--227, March 1983.
• 7: C. H. Stapper, "Modeling of Integrated Circuit Defect Sensitivities," IBM Journal of Research and Development, vol. 27, no. 6, pp. 549--557, Nov. 1983.
• 8: D. Schmitt-Landsiedel, D. Keitel-Schulz, J. Khare, S. Griep and W Maly, "Critical Area Analysis for Design Based Yield Improvements of VLSI Circuits," Quality and Reliability Engineering International, vol. 11, pp. 225--232, 1995.
• 9: D. J. Ciplickas, X. Li and A. J. Strojwas, "Predictive Yield Modeling of VLSICs," Proc. of International Workshop on Statistical Metrology, pp. 28--37, 2000.
• 10: P. Simon, "Yield Modeling for Deep Sub-Micron IC Design," Ph.D. Thesis, Technical University of Eindhoven, 2001.
• 11: Gerard A. Allan , Anthony J. Walton, Efficient Critical Area Algorithms and Their Application to Yield Improvement and Test Strategies, Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, p.88-96, October 17-19, 1994
• 12: C. H. Ouyang , W. A. Pleskacz , W. Maly, Extraction of critical areas for opens in large VLSI circuits, Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems, p.21, November 06-08, 1996
• 13: K. C. Y. Mei, "Bridging and Stuck-at Faults," IEEE Trans. on Computers, vol. 23, no. 7, pp. 720--727, July 1974.
• 14: R. D. Blanton, "Methods for Characterizing, Generating Test Sequences for, and Simulating Integrated Circuit Faults Using Fault Tuples and Related Systems and Computer Program Products," Dec. 2004, U. S. Patent No. 6,836,856.
• 15: K. N. Dwarakanath, "Fault Tuples: A Paradigm for Universal Test Analysis," Technology Report. CMU-CAD 01-21, Carnegie Mellon University, Nov. 2001.
• 16: P. K. Nag and W. Maly, "Yield Estimation of VLSI Circuits," Proc. of TECHCON 90, pp. 267--270, Oct. 1990.