| Communication architecture optimization: making the shortest path shorter in regular networks-on-chip |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Munich, Germany
SESSION: Communication-centric system-level synthesis for MPSoC
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Pages: 712 - 717
Year of Publication: 2006
ISBN:3-9810801-0-6
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European Design and Automation Association
3001 Leuven, Belgium, Belgium
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Downloads (6 Weeks): 11, Downloads (12 Months): 47, Citation Count: 2
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ABSTRACT
Network-on-Chip (NoC)-based communication represents a promising solution to complex on-chip communication problems. Due to their regular structure, mesh-like NoC architectures have become very popular recently. However, they have poor topological properties such as long inter-node distances. In this paper, we address this very issue and explore the potential of partial NoC customization to improve both static and dynamic properties of the network significantly, while minimally affecting its regularity. Precise energy measurements on an FPGA prototype show that the improvement in network properties is achieved without a significant penalty in area and communication energy consumption.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 2
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Umit Y. Ogras , Radu Marculescu , Hyung Gyu Lee , Puru Choudhary , Diana Marculescu , Michael Kaufman , Peter Nelson, Challenges and Promising Results in NoC Prototyping Using FPGAs, IEEE Micro, v.27 n.5, p.86-95, September 2007
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