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Communication architecture optimization: making the shortest path shorter in regular networks-on-chip
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe: Proceedings table of contents
Munich, Germany
SESSION: Communication-centric system-level synthesis for MPSoC table of contents
Pages: 712 - 717  
Year of Publication: 2006
ISBN:3-9810801-0-6
Authors
Umit Y. Ogras  Carnegie Mellon University
Radu Marculescu  Carnegie Mellon University
Hyung Gyu Lee  Seoul National University, Korea
Naehyuck Chang  Seoul National University, Korea
Sponsors
: The EDA Consortium
EDAA : European Design and Automation Association
IEEE-CS\DATC : The IEEE Computer Society
Publisher
European Design and Automation Association  3001 Leuven, Belgium, Belgium
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Downloads (6 Weeks): 11,   Downloads (12 Months): 47,   Citation Count: 2
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ABSTRACT

Network-on-Chip (NoC)-based communication represents a promising solution to complex on-chip communication problems. Due to their regular structure, mesh-like NoC architectures have become very popular recently. However, they have poor topological properties such as long inter-node distances. In this paper, we address this very issue and explore the potential of partial NoC customization to improve both static and dynamic properties of the network significantly, while minimally affecting its regularity. Precise energy measurements on an FPGA prototype show that the improvement in network properties is achieved without a significant penalty in area and communication energy consumption.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Umit Y. Ogras: colleagues
Radu Marculescu: colleagues
Hyung Gyu Lee: colleagues
Naehyuck Chang: colleagues