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Cell delay analysis based on rate-of-current change
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe: Proceedings table of contents
Munich, Germany
SESSION: Timing and noise analysis table of contents
Pages: 539 - 544  
Year of Publication: 2006
ISBN:3-9810801-0-6
Authors
Shahin Nazarian  University of Southern California
Massoud Pedram  University of Southern California
Sponsors
: The EDA Consortium
EDAA : European Design and Automation Association
IEEE-CS\DATC : The IEEE Computer Society
Publisher
European Design and Automation Association  3001 Leuven, Belgium, Belgium
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ABSTRACT

A cell delay model based on rate-of-current-change is presented, which accounts for the impact of the shape of the noisy waveform on the output voltage waveform. More precisely, a pre-characterized table of time derivatives of the output current as a function of input voltage and output load values is constructed. The data in this table, in combination with the Taylor series expansion of the output current, is utilized to progressively compute the output current waveform, which is then integrated to produce the output voltage waveform. Experimental results show the effectiveness and efficiency of this new delay model.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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M. Hashimoto, Y. Yamada, H. Onodera, "Equivalent waveform propagation for static timing analysis," IEEE Trans. Computer-Aided Design of Integ. Circuits & Systems, Vol. 23, No.4, pp. 498--508, 2004.
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P. Buch, W. J. Dai "Understanding ECSM and CCSM," http://www.magma-da.com/c/@SQJEgjiSilJ_6/Pages/MWAUnderstandingECSMandCCSM.html.
 
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"Hspice: The golden standard for Accurate Circuit Simulation," http://www.synopsys.com/products/mixedsignal/hspice/hspice.html.
Collaborative Colleagues:
Shahin Nazarian: colleagues
Massoud Pedram: colleagues