Software-based self-test of processors under power constraints

ABSTRACT

Software-based self-test (SBST) of processors offers many benefits, such as dispense with expensive test equipments, test execution during maintenance and in the field or initialization tests for the whole system. In this paper, for the first time a structural SBST methodology is proposed which optimizes energy, average power consumption, test length and fault coverage at the same time.

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INDEX TERMS

Keywords:
low power test, processor test, test program generation