Automating processor customisation: optimised memory access and resource sharing

ABSTRACT

We propose a novel methodology to generate Application Specific Instruction Processors (ASIPs) including custom instructions. Our implementation balances performance and area requirements by making custom instructions reusable across similar pieces of code. In addition to arithmetic and logic operations, table look-ups within custom instructions reduce costly accesses to global memory. We present synthesis and cycle-accurate simulation results for six embedded benchmarks running on customised processors. Reusable custom instructions achieve an average 319% speedup with only 5% additional area. The maximum speedup of 501% for the Advanced Encryption Standard (AES) requires only 3.6% additional area.

REFERENCES

• 1: Melvin A. Breuer, Generation of optimal code for expressions via factorization, Communications of the ACM, v.12 n.6, p.333-340, June 1969 [doi>10.1145/363011.363153]
• 2: Philip Brisk , Adam Kaplan , Ryan Kastner , Majid Sarrafzadeh, Instruction generation and regularity extraction for reconfigurable processors, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France [doi>10.1145/581630.581672]
• 3: D. C. Burger and T. M. Austin. The SimpleScalar tool set.
• 4: A. Fauth et al. Generation of hardware machine models from instruction set descriptions. In Proc. IEEE Workshop VLSI Signal Proc., Veldhoven (Netherlands), pages 242--250, October 1993.
• 5: Gunnar Braun , Achim Nohl , Weihua Sheng , Jianjiang Ceng , Manuel Hohenauer , Hanno Scharwächter , Rainer Leupers , Heinrich Meyr, A novel approach for flexible and consistent ADL-driven ASIP design, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996763]
• 6: Kubilay Atasu , Laura Pozzi , Paolo Ienne, Automatic application-specific instruction-set extensions under microarchitectural constraints, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775897]
• 7: M. R. Guthaus , J. S. Ringenberg , D. Ernst , T. M. Austin , T. Mudge , R. B. Brown, MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on, p.3-14, December 02-02, 2001 [doi>10.1109/WWC.2001.15]
• 8: Partha Biswas , Vinay Choudhary , Kubilay Atasu , Laura Pozzi , Paolo Ienne , Nikil Dutt, Introduction of local memory elements in instruction set extensions, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996765]
• 9: V. V. Goldman and J. A. van Hulzen. Automatic code vectorisation of arithmetic expressions by bottom-up structure recognition. In Computer Algebra and Parallelism, pages 119--132. 1989.
• 10: F. Sun, S. Ravi, and N. K. Jha. Custom-instruction synthesis for extensible-processor platforms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(2):216--228, February 2004.