Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation

ABSTRACT

This paper presents a systematic and optimal design of hybrid cascode compensation method which is used in fully differential two-stage CMOS operational transconductance amplifiers (OTAs). The closed loop analysis results are given to obtain a design procedure. A simple design procedure for the minimum settling time of the hybrid cascode compensation technique for a two-stage class A/AB amplifier is proposed. Optimal design issues of power dissipation are considered to achieve the lowest power consumption for the required settling time. Finally, a design example is presented to show both the usefulness of the hybrid cascode compensation and the proposed design procedure. The proposed design technique can help circuit designers as well as it can be used in computer aided circuit design tools.

REFERENCES

• 1: B. Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw-Hill, 2001.
• 2: B. K. Ahuja, "An improved frequency compensation technique for CMOS operational amplifiers," IEEE J. Solid-State Circuits, vol. 18, no. 6, pp. 629--633, Dec. 1983.
• 3: D. B. Ribner and M. A. Copeland, "Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range," IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp. 919--925, Dec. 1984.
• 4: Mohammad Yavari , Omid Shoaei, Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871592]
• 5: M. Yavari and O. Shoaei, "Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications," IEE Proc. Circuits, Devices, and Systems, vol. 151, pp. 573--578, Dec. 2004.
• 6: L. Yao, M. Steyaert, and W. Sansen, "Fast-settling CMOS two-stage operational transconductance amplifiers and their systematic design," Proc. ISCAS, vol. 2, pp 839--842, May 2002.
• 7: M. Yavari, "Hybrid cascode compensation for two-stage CMOS opamps," IEICE Trans. Electron., vol. E88-C, no. 6, pp. 1161--1165, June 2005.
• 8: S. Rabii and B. A. Wooley, "A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 783--796, June 1997.
• 9: A. Feldman, High-speed, low-power sigma-delta modulators for RF baseband channel applications, Ph.D. Dissertation, University of California, Berkeley, CA, 1997.
• 10: Reza Lotfi , Mohammad Taherzadeh-Sani , M. Yaser Azizi , Omid Shoaei, A low-power design methodology for high-resolution pipelined analog-to-digital converters, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871590]