Two-phase resonant clocking for ultra-low-power hearing aid applications

ABSTRACT

Resonant clocking holds the promise of trading speed for energy in CMOS circuits that can afford to operate at low frequency, like hearing aids. An experimental chip with 110k transistors and more than 2500 latches, has been designed, fabricated and tested. The measured energy consumption of the design at 0.8 V is 62 μW/MHz, about 7.5% less than the conventional single-edge-triggered benchmark. Closer analysis reveals that much of the energy savings brought about by resonant clocking at low supply voltages are lost when a CMOS circuit is operated at higher voltages. This is because of the crossover currents that persist for much of a clock period when a circuit is driven from sine-type clock waveform.

REFERENCES

• 1: P. Mosch, G. van Oerle, S. Menzl, N. Rougnon-Glasson, K. van Nieuwenhove, and M. Wezelenburg, "A 660-μW 50-Mops 1-V DSP for a hearing aid chip set," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1705--1712, Nov. 2000.
• 2: A. J. Drake, K. J. Nowka, T. Y. Nguyen, J. L. Burns, and R. B. Brown, "Resonant clocking using distributed parasitic capacitance," IEEE J. Solid-State Circuits, vol. 39, pp. 1520--1528, Sept. 2004.
• 3: W. C. Athas, N. Tzartzanis, N. Svensson, and L. Peterson, "A low-power microprocessor based on resonant energy," IEEE J. Solid-State Circuits, vol. 32, pp. 1693--1701, Aug. 1997.
• 4: W. Athas, N. Tzartzanis, W. Mao, L. Peterson, K. Lal, K. Chong, J. S. Moon, L. Svensson, and M. Bolotski, "The design and implementation of a low-power clock-powered microprocessor," IEEE J. Solid-State Circuits, vol. 35, pp. 1561--1570, Nov. 2000.
• 5: Joong-Seok Moon , William C. Athas , Sigfrid D. Soli , Jeffrey T. Draper , Peter A. Beerel, Voltage-pulse driven harmonic resonant rail drivers for low-power applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.762-777, October 2003 [doi>10.1109/TVLSI.2003.814323]
• 6: Muhammad Arsalan , Maitham Shams, Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits, Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), p.171-174, January 03-07, 2005 [doi>10.1109/ICVD.2005.64]
• 7: Anantha P. Chandrakasan , Robert W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, Norwell, MA, 1995
• 8: H. Mahmoodi-Meimand and A. Afzali-Kusha, "Efficient power clock generation for adiabatic logic," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS'01), Sydney, Australia, May 2001, pp. 642--645.
• 9: F. Carbognani, F. Buergin, N. Felber, H. Kaeslin, and W. Fichtner, "Two-phase clocking and a new latch design for low-power portable applications," in Proc. Power and Timing Modeling, Optimization and Simulation (PATMOS'05), Leuven, Belgium, Sept. 2005, pp. 446--455.