Analysis of the impact of bus implemented EDCs on on-chip SSN

ABSTRACT

In this paper we analyze the impact of error detecting codes, implemented on an on-chip bus, on the on-chip simultaneous switching noise (SSN). First, we analyze in detail how SSN is impacted by different bus transitions, pointing out its dependency on the number and placement of switching wires. Afterwards, we present an analytical model that we have developed in order to estimate the SSN, and that we prove to be very accurate in SSN prediction. Finally, by employing the developed model, we estimate the SSN due to different EDCs implemented on an on-chip bus. In particular, we highlight how their differences in the number of switching wires, bus parallelism and codewords influence the on-chip SSN.

REFERENCES

• 1: Semiconductor Industry Assoc., San Jose, Calif. The 2003 National Technology Roadmap for Semiconductors, 2003.
• 2: Xavier Aragonès , Jose Luis González , Francesc Moll , Antonio Rubio, Noise Generation and Coupling Mechanisms in Deep-Submicron ICs, IEEE Design & Test, v.19 n.5, p.27-35, September 2002 [doi>10.1109/MDT.2002.1033789]
• 3: SimultaneouG. Bai and I. Hajjs Switching Noise and Resonance Analysis of On-Chip Power Distribution Network, Proceedings of the 3rd International Symposium on Quality Electronic Design, p.163, March 18-21, 2002
• 4: F. Caignet, S. Delmas-Bendhia, and E. Sicard. The Challenge of Signal Integrity in Deep-Submicrometer CMOS Technology. Proc. of IEEE, pages 556 -- 573, April 2001.
• 5: Yi-Shing Chang , Sandeep K. Gupta , Melvin A. Breuer, Analysis of Ground Bounce in Deep Sub-Micron Circuits, Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), p.110, April 27-May 01, 1997
• 6: C. L. Chen , Brian W. Curran, Switching Codes for Delta-I Noise Reduction, IEEE Transactions on Computers, v.45 n.9, p.1017-1021, September 1996 [doi>10.1109/12.537124]
• 7: Michele Favalli , Cecilia Metra, Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.3, p.392-396, Sept. 1999 [doi>10.1109/92.784100]
• 8: Rajamohana Hegde , Naresh R. Shanbhag, Toward achieving energy efficiency in presence of deep submicron noise, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.4, p.379-391, Aug. 2000 [doi>10.1109/92.863617]
• 9: Payam Heydari , Massoud Pedram, Ground bounce in digital VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.180-193, April 2003 [doi>10.1109/TVLSI.2003.810785]
• 10: Parag K. Lala, Self-checking and fault-tolerant digital design, Morgan Kaufmann Publishers Inc., San Francisco, CA, 2000
• 11: Andre K. Nieuwland , Atul Katoch , Daniele Rossi , Cecilia Metra, Coding Techniques for Low Switching Noise in Fault Tolerant Busses, Proceedings of the 11th IEEE International On-Line Testing Symposium, p.183-189, July 06-08, 2005 [doi>10.1109/IOLTS.2005.19]
• 12: Dhiraj K. Pradhan, Fault-tolerant computing: theory and techniques; vol. 1, Prentice-Hall, Inc., Upper Saddle River, NJ, 1986
• 13: D. Rossi , A. Muccio , A. K. Nieuwland , A. Katoch , C. Metra, Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems, Proceedings of the International On-Line Testing Symposium, 10th IEEE (IOLTS'04), p.135, July 12-14, 2004 [doi>10.1109/IOLTS.2004.26]
• 14: Jaume Segura , Charles F. Hawkins, CMOS Electronics: How It Works, How It Fails, John Wiley & Sons, 2004
• 15: Kevin T. Tang , Eby G. Friedman, Simultaneous switching noise in on-chip CMOS power distribution networks, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.4, p.487-493, August 2002 [doi>10.1109/TVLSI.2002.800533]