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Time domain model order reduction by wavelet collocation method
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe: Proceedings table of contents
Munich, Germany
SESSION: Power grid and large interconnect network analysis table of contents
Pages: 21 - 26  
Year of Publication: 2006
ISBN:3-9810801-0-6
Authors
Xuanzeng  Fudan University, Shanghai, China
Lihong Feng  Fudan University, Shanghai, China
Yangfeng Su  Fudan University, Shanghai, China
Wei Cai  University of North Carolina at Charlotte, Charlotte, NC
Dian Zhou  University of Texas at Dallas, Richardson, TX
Charles Chiang  Synopsys Inc., Mountain View, CA
Sponsors
: The EDA Consortium
EDAA : European Design and Automation Association
IEEE-CS\DATC : The IEEE Computer Society
Publisher
European Design and Automation Association  3001 Leuven, Belgium, Belgium
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ABSTRACT

In this paper, a wavelet based approach is proposed for the model order reduction of linear circuits in time domain. Compared with Chebyshev reduction method, the wavelet reduction approach can achieve smaller reduced order circuits with very high accuracy, especially for those circuits with strong singularities. Furthermore, to compute the basis function coefficient vectors, a fast Sylvester equation solver is proposed, which works more than one or two orders faster than the vector equation solver employed by Chebyshev reduction method. The proposed wavelet method is also compared with the frequency domain model reduction method, which may loose accuracy in time domain. Both theoretical analysis and experiment results have demonstrated the high speed and high accuracy of the proposed method.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Roland W. Freund, Reduced-Order Modeling Techniques Based on Krylov Subspaces and Their Use in Circuit Simulation, Numerical Analysis Manuscript No. 98-3-02, Bell Laboratories, Murray Hill, New Jersey, Feb. 1998.
 
2
 
3
D. Zhou and W. Cai, "A Fast Wavelet Collocation Method for High-Speed Circuit Simulation", IEEE Trans. Circuits and Systems, vol. 46, no. 8, pp. 920--930, Aug. 1999.
 
4
D. Zhou, W. Cai and W. Zhang "An Adaptive Wavelet Method For Nonlinear Circuit Simulation", IEEE Trans. Circuits and Systems, vol. 46, no. 8, pp. 931--938, Aug. 1999.
5
 
6
Xuan Zeng, Sheng Huang, Yangfeng Su and Dian Zhou "An Efficient Sylvester Equation Solver for Time Domain Circuit Simulation By Wavelet Collocation Method", IEEE ISCAS, vol. III, pp. 168--171, May, 2003.
 
7
G. H. Golub, S. Nash and C. Van Loan, "A Hessenberg-Schur Method for the Problem AX+XB=C", IEEE Tran. Automatic Control, Vol. Ac-24, No.6, Dec. 1979.
 
8
Janet Meiling Wang, Chia-Chi Chu, Qingjian Yu and Ernest S. Kuh, "On Projection-Based Algorithms for Model-Order Reduction of Interconnects", IEEE Tran on Circuit and Systems-I, Vol.49, No. 11, Nov. 2002.
Collaborative Colleagues:
Xuanzeng: colleagues
Lihong Feng: colleagues
Yangfeng Su: colleagues
Wei Cai: colleagues
Dian Zhou: colleagues
Charles Chiang: colleagues