| Efficient link capacity and QoS design for network-on-chip |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Munich, Germany
SESSION: Allocation and scheduling for MPSoCs and NoCs
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Pages: 9 - 14
Year of Publication: 2006
ISBN:3-9810801-0-6
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Authors
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Zvika Guz
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Technion, Haifa, Israel
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Isask'har Walter
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Technion, Haifa, Israel
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Evgeny Bolotin
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Technion, Haifa, Israel
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Israel Cidon
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Technion, Haifa, Israel
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Ran Ginosar
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Technion, Haifa, Israel
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Avinoam Kolodny
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Technion, Haifa, Israel
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European Design and Automation Association
3001 Leuven, Belgium, Belgium
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Downloads (6 Weeks): 12, Downloads (12 Months): 85, Citation Count: 6
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ABSTRACT
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-of-Service timing constraints.First, we introduce a novel analytical delay model for virtual channeled wormhole networks with non-uniform link capacities that eliminates costly simulations at the inner-loop of the optimization process. Second, we present an efficient capacity allocation algorithm that assigns link capacities such that packet delays requirements for each flow are satisfied. We demonstrate the benefit of capacity allocation for a typical system on chip, where the traffic is heterogeneous and delay requirements may largely vary, in comparison with the standard approach which assumes uniform-capacity links.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 6
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Evgeny Bolotin , Israel Cidon , Ran Ginosar , Avinoam Kolodny, Routing table minimization for irregular mesh NoCs, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
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