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STAX: statistical crosstalk target set compaction
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe: Designers' forum table of contents
Munich, Germany
SESSION: On chip communication networks table of contents
Pages: 172 - 177  
Year of Publication: 2006
ISBN ~ ISSN:478061 , 3-9810801-0-6
Authors
Shahin Nazarian  University of Southern California
Massoud Pedram  University of Southern California
Sandeep K. Gupta  University of Southern California
Melvin A. Breuer  University of Southern California
Sponsors
EDAA : European Design and Automation Association
: The EDA Consortium
IEEE-CS\DATC : The IEEE Computer Society
Publisher
European Design and Automation Association  3001 Leuven, Belgium, Belgium
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ABSTRACT

This paper presents STAX, a crosstalk target set compaction framework to reduce the complexity of the crosstalk ATPG process by pruning non-fault-producing targets. In general, existing pruning techniques do not employ their processes in a cost-effective manner. Neither do they handle process variations properly. To address the first weakness, this paper presents a framework to determine a sequence of available analysis and pruning tool invocations to prune as many of the crosstalk targets as fast as possible. As a result, an initially enormous collection of crosstalk targets is usually reduced to a very small set of targets via a vectorless process. A statistical static timing analyzer is developed and embedded to address the second shortcoming of existing approaches. Experimental results on ISCAS'85 benchmark demonstrate that STAX greatly improves the runtime compared to other crosstalk target pruning methodologies, including ATPG, with no prior target set compaction.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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H. Takahashi, K. J. Keller, K. T. Le, K. K. Saluja, Y. Takamatsu, "A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits," IEEE Trans. on CAD, Vol. 24, Issue 2, pp. 252--263, Feb. 2005.
 
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J. H. Chern, J. Huang, L. Arledge, P. C. Li, P. Yang, "Multilevel metal capacitance models for CAD design synthesis systems," IEEE Electron Device Letters, Vol. 13, Issue 1, pp. 32--34, Jan. 1992.
 
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D. Blaauw, V. Zolotov, S. Sundareswaran, "Slope propagation in static timing analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1180--1195, 2002.

Collaborative Colleagues:
Shahin Nazarian: colleagues
Massoud Pedram: colleagues
Sandeep K. Gupta: colleagues
Melvin A. Breuer: colleagues