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Software implementation of Tate pairing over GF(2m)
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe: Designers' forum table of contents
Munich, Germany
SESSION: Secure and security systems table of contents
Pages: 7 - 11  
Year of Publication: 2006
ISBN ~ ISSN:478061 , 3-9810801-0-6
Authors
G. Bertoni  ST Microelectronics, Via Olivetti, Agrate B., Milano, Italy - Piazza L. Da Vinci, Milano, Italy
L. Breveglieri  Politecnico di Milano, Via Olivetti, Agrate B., Milano, Italy - Piazza L. Da Vinci, Milano, Italy
P. Fragneto  ST Microelectronics, Via Olivetti, Agrate B., Milano, Italy - Piazza L. Da Vinci, Milano, Italy
G. Pelosi  Politecnico di Milano, Via Olivetti, Agrate B., Milano, Italy - Piazza L. Da Vinci, Milano, Italy
L. Sportiello  ST Microelectronics, Via Olivetti, Agrate B., Milano, Italy - Piazza L. Da Vinci, Milano, Italy
Sponsors
EDAA : European Design and Automation Association
: The EDA Consortium
IEEE-CS\DATC : The IEEE Computer Society
Publisher
European Design and Automation Association  3001 Leuven, Belgium, Belgium
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ABSTRACT

Recently, the interest about the Tate pairing over binary fields has decreased due to the existence of efficient attacks to the discrete logarithm problem in the subgroups of such fields. We show that the choice of fields of large size to make these attacks infeasible does not lead to a degradation of the computation performance of the pairing. We describe and evaluate by simulation an implementation of the Tate pairing that allows to achieve good timing results, comparable with those reported in the literature but with a higher level of security.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
G. Bertoni: colleagues
L. Breveglieri: colleagues
P. Fragneto: colleagues
G. Pelosi: colleagues
L. Sportiello: colleagues