VICTORIA: VMX indirect compute technology oriented towards in-line acceleration

ABSTRACT

There is increasing interest in the use of accelerators in computer systems. Accelerators are processor-attached hardware units that can perform certain functions faster than the conventional general purpose processor. In this paper, we describe the VICTORIA PowerPC architecture, which is based on the iVMX accelerator technology. The iVMX accelerator extends the existing VMX architecture with indirect register addressing. That approach greatly extends the architected space of registers and opens the door for highly optimized vector algorithms that can sustain very high processing rates. The large space of registers is directly controlled by the executing code and offers a sufficiently large storage to hold sizeable intermediate results. This helps reduce the negative effects of limited memory bandwidth and high memory latency. The iVMX accelerator is an example of in-line accelerator; that is, the instructions that drive the accelerator are part of the same stream that drives the main processor. Compared to off-line accelerators, which execute their own instruction stream, in-line accelerators present a much more convenient programming model.

REFERENCES

• 1: IBM Corporation. PowerPC Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual. Ver. 2.06, 22 Aug. 2005.
• 2: Intel Corporation. Intel® Itanium® Architecture Software Developer's Manual, Vol. 2: System Architecture. Oct. 2002.
• 3: http://www-128.ibm.com/developerworks/power/library/pa-cellperf/.
• 4: Gary S. Tyson , Mikhail Smelyanskiy , Edward S. Davidson, Evaluating the Use of Register Queues in Software Pipelined Loops, IEEE Transactions on Computers, v.50 n.8, p.769-783, August 2001 [doi>10.1109/12.946998]
• 5: Tokuzo Kiyohara , Scott Mahlke , William Chen , Roger Bringmann , Richard Hank , Sadun Anik , Wen-Mei Hwu, Register connection: a new approach to adding registers into instruction set architectures, Proceedings of the 20th annual international symposium on Computer architecture, p.247-256, May 16-19, 1993, San Diego, California, United States
• 6: J. H. Moreno , V. Zyuban , U. Shvadron , F. D. Neeser , J. H. Derby , M. S. Ware , K. Kailas , A. Zaks , A. Geva , S. Ben-David , S. W. Asaad , T. W. Fox , D. Littrell , M. Biberstein , D. Naishlos , H. Hunter, An innovative low-power high-performance programmable signal processor for digital communications, IBM Journal of Research and Development, v.47 n.2-3, p.299-326, March 2003
• 7: Cascaval, C. G. and Chatterjee, S. System and Method for Encoding and Decoding Architecture Registers. US Pat. Appl. 20050060520, 17 Mar. 2005.
• 8: Francisca Quintana , Jesus Corbal , Roger Espasa , Mateo Valero, Adding a vector unit to a superscalar processor, Proceedings of the 13th international conference on Supercomputing, p.1-10, June 20-25, 1999, Rhodes, Greece [doi>10.1145/305138.305148]
• 9: Roger Espasa , Federico Ardanaz , Joel Emer , Stephen Felix , Julio Gago , Roger Gramunt , Isaac Hernandez , Toni Juan , Geoff Lowney , Matthew Mattina , André Seznec, Tarantula: a vector extension to the alpha architecture, Proceedings of the 29th annual international symposium on Computer architecture, p.281, May 25-29, 2002, Anchorage, Alaska
• 10: Christoforos Kozyrakis , David Patterson, Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 11: N. P. Jouppi , J. Bertoni , D. W. Wall, A unified vector/scalar floating-point architecture, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.134-143, April 03-06, 1989, Boston, Massachusetts, United States
• 12: Chang, L., et. al. Stable SRAM cell design for the 32 nm node and beyond. In 2005 Symp. VLSI Tech. Dig. Of Tech. Papers (Kyoto, Japan, Jun. 2005). 128--129.
• 13: Derby, J. H. and Moreno, J. H. A high-performance embedded DSP with novel SIMD features. In Proc. ICASSP'03 (Hong Kong, Apr. 6 - 10, 2003), II - 301--304.
• 14: Dorit Naishlos , Marina Biberstein , Shay Ben-David , Ayal Zaks, Vectorizing for a SIMdD DSP architecture, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA [doi>10.1145/951710.951714]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Single-instruction-stream, multiple-data-stream processors (SIMD)

General Terms:
Design, Performance

Keywords:
SIMD, VMX, accelerators, powerPC