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ABSTRACT

A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs is presented. The minimum power consumption of these converters for a given specification has achieved by dynamically exploiting the slewing and partially settling regimes of the integrators, and analytical dynamic expression for maximum possible output swing of the OTAs, which are affected by scaling factors. The proposed, precise, and yet simple approach gives in rapid and efficient design of ADCs. In order to verify the usefulness of the proposed methodology a 14-bit, 5MS/s ADC has been realized in Hspice making use of a 0.18um CMOS technology. Simulation results show that there is a good agreement between the circuit performance and the predicted by the system level design methodology.

REFERENCES

• 1: J. Silva, U. Moon, and G.C. Temes, "Low-distortion Delta-Sigma Topologies for Mash Architectures," Proceeding of the IEEE Int. Symp. Cir. Syst, pp. 1144--1147, July 2004.
• 2: A. Marques, Peluso, M. Steyaert, and W. Sansen, "Analysis of the Trade-off between Bandwidth, Resolution, and Power in ΔΕ Analog to Digital Converters, Proceeding of the IEEE Int. Conference on Electronics. Cir. Syst, ICECS, Volume 2, pp. 153--156, Sept 1998.
• 3: R. Naiknaware, T. Fiez "Power Optimization of ΔΕAnalog-to-Digital Converters Based on Slewing and Partial Settling Considerations," Proceeding of the IEEE Int. Symp. Cir. Syst, pp. 360--364, June 1998.
• 4: Reza Lotfi , Mohammad Taherzadeh-Sani , M. Yaser Azizi , Omid Shoaei, Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.371, November 09-13, 2003 [doi>10.1109/ICCAD.2003.136]
• 5: V. Majidzadeh, O. Shoaei, "A Modified Efficient Reduced-Sample-rate Delta-Sigma-Pipeline ADC Architecture" Proceeding of the IEEE Int. Midwest. Symp. Cir. Syst, pp 527--830, Aug 2005.
• 6: P. J. M. Laarhoven , E. H. L. Aarts, Simulated annealing: theory and applications, Kluwer Academic Publishers, Norwell, MA, 1987

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Algorithms, Design, Performance

Keywords:
power optimization, reduced-sample-rate architectures, sigma-delta-pipeline ADCs