| Using Lin-Kernighan algorithm for look-up table compression to improve code density |
| Full text |
Pdf
(360 KB)
|
| Source
|
Great Lakes Symposium on VLSI
archive
Proceedings of the 16th ACM Great Lakes symposium on VLSI
table of contents
Philadelphia, PA, USA
SESSION: System and architectural-Level VLSI design
table of contents
Pages: 259 - 265
Year of Publication: 2006
ISBN:1-59593-347-6
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 13, Downloads (12 Months): 57, Citation Count: 4
|
|
|
ABSTRACT
The presented work uses code compression to improve the design efficiency of an embedded system. In particular, we present a method and architecture for compressing the so-called Look-up Tables that are necessary for the de-compression process. No other work has yet focused on minimizing the Look-up Tables that, as we show, have a significant impact on the total overhead of a hardware-based decompression scheme. We introduce a novel and very efficient hardware-supported approach based on Canonical Huffman Coding. Using the Lin-Kernighan algorithm we reduce the Look-up Table size by up to 45%. As a result, we achieve all-over compression ratios as low as 45% (already including the overhead of the Look-up Tables). Thereby, our scheme is entirely orthogonal to approaches that take particularities of a certain instruction set architecture into account, meaning that compression could be further improved. Factoring in the orthogonality, our scheme is the basis for not-yet-achieved efficiency in hardware-supported compression schemes. We have conducted evaluations using a representative set (in terms of size and application domain) of applications and have applied it to three major embedded processor architectures, namely ARM, MIPS and PowerPC. The hardware evaluation shows no performance penalty.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
T. O. at el. Instruction encoding techniques for area minimization of instruction rom. ISSS, 1998.
|
| |
3
|
|
 |
4
|
|
| |
5
|
|
 |
6
|
|
| |
7
|
D. Das, R. Kumar, and P. Chakrabarti. Code compression using unused encoding space for variable length instruction encodings. 8th VLSI Design & Test Workshop, Aug. 2004.
|
| |
8
|
|
| |
9
|
M. B. Game. Codepack: Code compression for powerpc processors. PowerPC Embedded Processor Solutions, 2000.
|
| |
10
|
K. Helsgaun. An effective implementation of the lin-kernighan traveling salesman heuristic. European Journal of Operational Research, 2000.
|
| |
11
|
|
| |
12
|
Charles Lefurgy , Peter Bird , I-Cheng Chen , Trevor Mudge, Improving code density using compression techniques, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.194-203, December 01-03, 1997, Research Triangle Park, North Carolina, United States
|
| |
13
|
|
| |
14
|
H. Lekatsas and W. Wolf. Samc: A code compression algorithm for embedded processors. IEEE Transactions on CAD, 1999.
|
| |
15
|
|
| |
16
|
|
| |
17
|
M. K. Rudberg and L. Wainhamar. High speed pipeline parallel huffman decoding. IEEE International Symposium on Circuits and Systems, 1997.
|
| |
18
|
|
| |
19
|
I. Tuduce and T. Gross. Adaptive main memory compression. Proc. USENIX Conf., Apr. 2005.
|
 |
20
|
|
 |
21
|
|
 |
22
|
Lei Yang , Robert P. Dick , Haris Lekatsas , Srimat Chakradhar, CRAMES: compressed RAM for embedded systems, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, p.93-98, September 19-21, 2005, Jersey City, NJ, USA
[doi> 10.1145/1084834.1084861]
|
 |
23
|
Yukihiro Yoshida , Bao-Yu Song , Hiroyuki Okuhata , Takao Onoye , Isao Shirakawa, An object code compression approach to embedded processors, Proceedings of the 1997 international symposium on Low power electronics and design, p.265-268, August 18-20, 1997, Monterey, California, United States
[doi> 10.1145/263272.263349]
|
|