Towards formal probabilistic power-performance design space exploration

ABSTRACT

We describe a formal probabilistic power-performance design space exploration technique. The technique aims at enabling hierarchical design space exploration based on a fully probabilistic description of power-performance tradeoffs. Probabilistic Pareto sets in power-performance space are proposed as canonical encodings of the power and delay tradeoffs in designs under any source of uncertainty. An algorithm to compute a composite probabilistic power-performance Pareto set for series or parallel connections of circuit blocks is also developed and validated. The algorithm is based on numerical convolution and is suitable for micro-architecture pipeline design exploration in the presence of process variability.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

Additional Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.0 General

General Terms:
Design, Performance, Reliability

Keywords:
canonical representation, formal methodology, hierarchical design exploration, performance, power, probabilistic