Maximum effective distance of on-chip decoupling capacitors in power distribution grids

ABSTRACT

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the available white space on a die. The efficacy of on-chip decoupling capacitors depends upon the impedance of the power/ground lines connecting the capacitors to the current loads and power supplies. A maximum effective radius exists for each on-chip decoupling capacitor. Beyond this effective distance, a decoupling capacitor is completely ineffective. Two effective radii determined by the target impedance (during discharge) and charge time are presented in this paper. Depending upon the parasitic impedance of the power distribution system, the maximum voltage drop as seen at the current load is achieved either at the first droop or at the end of the switching activity (the second droop). Two criteria to estimate the minimum required on-chip decoupling capacitance are developed based on the critical parasitic impedance. To be effective, the decoupling capacitor has to be fully charged before the next switching event. A design space is described that characterizes the tolerable parasitic resistances and inductances, while restoring the charge on the decoupling capacitor within a target charge time. An overall design methodology for placing on-chip decoupling capacitors is presented in this paper. It is shown that for an on-chip decoupling capacitor to be effective, both effective radii criteria should be simultaneously satisfied.

REFERENCES

• 1: International Technology Roadmap for Semiconductors, 2004 Update, 2004. Semiconductor Industry Association.
• 2: A. V. Mezhiba and E. G. Friedman, Power Distribution Networks in High Speed Integrated Circuits, Kluwer Academic Publishers, 2004.
• 3: Andrey V. Mezhiba , Eby G. Friedman, Scaling trends of on-chip power distribution noise, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.4, p.386-394, April 2004 [doi>10.1109/TVLSI.2004.825834]
• 4: L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, "Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology," IEEE Transactions on Advanced Packaging, Vol. 22, No. 3, pp. 284--291, August 1999.
• 5: Sani R. Nassif , Onsi Fakhouri, Technology trends in power-grid-induced noise, Proceedings of the 2002 international workshop on System-level interconnect prediction, April 06-07, 2002, San Diego, California, USA [doi>10.1145/505348.505360]
• 6: W. D. Becker et al., "Modeling, Simulation and Measurement of Mid-Frequency Simultaneous Switching Noise in Computer Systems," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, Vol. 21, Issue 2, pp. 157--163, May 1998.
• 7: M. E. Van Valkenburg, Network Analysis, Prentice-Hall, 1974.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.m Miscellaneous

General Terms:
Design

Keywords:
decoupling capacitors, power distribution grids, power distribution systems