Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology

ABSTRACT

This paper presents a systematic design for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the target asynchronous circuits on one planar device layer which is fabricated with aggressive technology, are built on fault tolerant graph models with extra spare resources, and can be reconfigured by autonomous reconfiguration logic on another planar device layer which is fabricated with conservative technology, in the presence of hard errors. The yield analysis shows that this method can result in 20--30% overall yield enhancement. This design methodology can be conveniently applied to clocked designs without significant changes.

REFERENCES

• 1: Y. Zorian. Optimizing manufacturability by design for yield. In Proc. IEEE/CPMT/SEMI International Electronics Manufacturing Technology Symposium, 2004.
• 2: Song Peng , Rajit Manohar, Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration, Proceedings of the 2005 International Conference on Computer Design, p.171-179, October 02-05, 2005 [doi>10.1109/ICCD.2005.56]
• 3: K. Banerjee, S. J. Souri and P. Kapur et.al.. 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proceedings of the IEEE, 89(5), 2001.
• 4: I. Koren and Z. Koren. Defect Tolerance in VLSI Circuits: Techniques and Yield Analysis. Proceedings of the IEEE, 86(9), 1998.
• 5: A. V. Ferris-Prabhu. Yield implications and scaling laws for submicrometer devices. IEEE Transactions on Semiconductor Manufacturing, 1(2), 1988.
• 6: K. Emerson, Asynchronous Design - An Interesting Alternative, Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, p.318, January 04-07, 1997
• 7: A. M. Lines. Pipelined Asynchronous Circuits. Master's thesis, California Institute of Technology, 1995.
• 8: Alain J. Martin , Andrew Lines , Rajit Manohar , Mika Nystroem , Paul Penzes , Robert Southworth , Uri Cummings, The Design of an Asynchronous MIPS R3000 Microprocessor, Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), p.164, September 15-16, 1997
• 9: Ilana David , Ran Ginosar , Michael Yoeli, Self-timed is self-checking, Journal of Electronic Testing: Theory and Applications, v.6 n.2, p.219-228, April 1995 [doi>10.1007/BF00993088]
• 10: R. Leveugle , Z. Koren , I. Koren , G. Saucier , N. Wehn, The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis, IEEE Transactions on Computers, v.43 n.12, p.1398-1406, December 1994 [doi>10.1109/12.338099]
• 11: Sy-Yen Kuo , W. Kent Fuchs, Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLAs, IEEE Transactions on Computers, v.41 n.2, p.221-226, February 1992 [doi>10.1109/12.123398]
• 12: Miron Abramovici , Charles Stroud , Marty Emmert, Using embedded FPGAs for SoC yield improvement, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514099]
• 13: C. E. Stroud. Yield Modeling for Majority Voting based Defect-Tolerant VLSI Circuits. Proc. IEEE Southeast Regional Conference, 1999.
• 14: N. R. Mahapatra, A. Tareen and S. V. Garimella. Comparison and Analysis of Delay Elements. Proc. the 45th Midwest Symposium on Circuits and Systems, 2002.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Design

Keywords:
3D integration, asynchronous circuits, defect tolerance, self-reconfiguration, yield