A new power-area efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10Gb/s serial links

ABSTRACT

A new area-power efficient 4-PAM full-clock pre-emphasis CMOS transmitter for 10-Gb/s serial links is proposed. The transmitter reduces the chip area and power consumption by minimizing the number of DACs for 4-PAM pre-emphasis and the DC power consumption of each DAC. The number of DACs is set by the number of pre-emphasis taps and is independent of the number of parallel bits. The power consumption of each DAC is lowered by modulating the DC current in accordance with the level of output currents. A new full-clock multiplexing scheme is proposed to double the data rate of the widely used half-clock scheme without increasing the clock frequency. The transmitter is implemented in TSMC 0.18μm 1.8V CMOS technology and analyzed using SpectreRFM from Cadence Design Systems with BSIM3.3V transistor models and microstrip lines for channels. Simulation results are presented.

REFERENCES

• 1: William J. Dally , John Poulton, Transmitter Equalization for 4-GBPS Signaling, IEEE Micro, v.17 n.1, p.48-56, January 1997 [doi>10.1109/40.566199]
• 2: Mark Horowitz , Chih-Kong Ken Yang , Stefanos Sidiropoulos, High-Speed Electrical Signaling: Overview and Limitations, IEEE Micro, v.18 n.1, p.12-24, January 1998 [doi>10.1109/40.653013]
• 3: D. Foley and M. Flynn, "A low-power 8-PAM serial transceiver in 0.5 μm digital CMOS," IEEE JSSC, vol. 37, No. 3, pp. 310--316, Mar. 2002.
• 4: J. Liu and X. Lin, "Equalization in high-speed communication systems," IEEE Circuits and Systems Magazine, pp. 4--17, 2nd quarter, 2004.
• 5: M. Lee, W. J. Dally, and P. Chiang, "Low-power area-efficient high-speed I/O circuit techniques," IEEE JSSC, vol. 35, No. 11, pp. 1591--1599, Nov. 2000.
• 6: W. Dally and J. Poulton, "Transmitter equalization for 4 Gb/s signaling," in Proc. Hot Interconnects, pp. 29--39, Stanford Univ., Aug. 1996.
• 7: R. Farjad-Rad, C. Yang, M. Horowitz, and T. Lee, "A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter," IEEE JSSC, vol. 34, No. 4, pp. 580--585, May 1999.
• 8: R. Farjad-Rad, C. Yang, and M. Horowitz, "A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver," IEEE JSSC, vol. 35, No. 5, pp. 757--764, May 2000.
• 9: K. Farzan and D. Johns, "A CMOS 10-Gb/s power-efficient 4-PAM transmitter," IEEE JSSC, vol. 39, No. 3, pp. 529--532, March 2004.
• 10: J. Stonick, G. Wei, J. Sonntag, and D. Weinlader, "An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS," IEEE JSSC, vol. 38, No. 3, pp. 436--443, Mar. 2003.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS

General Terms:
Design

Keywords:
Gbps serial link transmitters